公开(公告)号：US20050104142A1

公开(公告)日：2005-05-19

申请号：US10712575

申请日：2003-11-13

申请人： Vijav Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

发明人： Vijav Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

IPC分类号： C23C16/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L29/76

CPC分类号： C23C16/34 ,  H01L21/28088 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/78

摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20 mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta—N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta—N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.

摘要翻译： 公开了Ta和N的化合物，潜在地包括其它元素，并且电阻率低于约20mOmegacm，并且N与Ta的元素比大于约0.9，用作场效应器件中的栅极材料。 这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下在含有介电层和高k电介质层的SiO 2 2上是稳定的，功函数接近n型Si的功函数。 金属Ta-N化合物通过化学气相沉积方法使用烷基亚氨基三（二烷基酰氨基）Ta种，例如叔戊酰亚胺基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。 沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。 用TaN或TaSiN处理的器件显示出接近理想的特性。

公开(公告)号：US20050250318A1

公开(公告)日：2005-11-10

申请号：US11180384

申请日：2005-07-13

申请人： Vijay Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

发明人： Vijay Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

IPC分类号： C23C16/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31 ,  H01L21/44 ,  H01L21/469 ,  H01L21/4763

CPC分类号： C23C16/34 ,  H01L21/28088 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/78

摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20 mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta—N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta—N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.

摘要翻译： 公开了Ta和N的化合物，潜在地包括其它元素，并且电阻率低于约20mOmegacm，并且N与Ta的元素比大于约0.9，用作场效应器件中的栅极材料。 这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下在含有介电层和高k电介质层的SiO 2 2上是稳定的，功函数接近n型Si的功函数。 金属Ta-N化合物通过化学气相沉积方法使用烷基亚氨基三（二烷基酰氨基）Ta种，例如叔戊酰亚胺基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。 沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。 用TaN或TaSiN处理的器件显示出接近理想的特性。

公开(公告)号：US20060246740A1

公开(公告)日：2006-11-02

申请号：US11119310

申请日：2005-04-29

申请人： Eduard Cartier ,  Matthew Copel ,  Supratik Guha ,  Richard Haight ,  Fenton McFeely ,  Vijay Narayanan

发明人： Eduard Cartier ,  Matthew Copel ,  Supratik Guha ,  Richard Haight ,  Fenton McFeely ,  Vijay Narayanan

IPC分类号： H01L21/31

CPC分类号： H01L21/823462 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/31691 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for removing charged defects from a material stack including a high k gate dielectric and a metal contact such that the final gate stack, which is useful in forming a pFET device, has a threshold voltage substantially within the silicon band gap and good carrier mobility. Specifically, the present invention provides a re-oxidation procedure that will restore the high k dielectric of a pFET device to its initial, low-defect state. It was unexpectedly determined that by exposing a material stack including a high k gate dielectric and a metal to dilute oxygen at low temperatures will substantially eliminate oxygen vacancies, resorting the device threshold to its proper value. Furthermore, it was determined that if dilute oxygen is used, it is possible to avoid undue oxidation of the underlying semiconductor substrate which would have a deleterious effect on the capacitance of the final metal-containing gate stack. The present invention also provides a semiconductor structure that includes at least one gate stack that has a threshold voltage within a control range and has good carrier mobility.

公开(公告)号：US20050269634A1

公开(公告)日：2005-12-08

申请号：US10863830

申请日：2004-06-04

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlO x N y Y。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：US20060275977A1

公开(公告)日：2006-12-07

申请号：US11500254

申请日：2006-08-07

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

公开(公告)号：US20050269635A1

公开(公告)日：2005-12-08

申请号：US10957342

申请日：2004-10-01

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure comprising a semiconductor substrate having source and drain diffusion regions located therein, the source and drain diffusion regions being separated by a device channel; and a gate stack located on top of the device channel, the gate stack comprising a high-k gate dielectric, an insulating interlayer and a fully silicided metal gate conductor, the insulating interlayer located between the high-k gate dielectric and the fully silicided metal gate conductor, wherein the insulating interlayer is capable of stabilizing threshold voltage and flatband voltage of the semiconductor structure to a targeted value.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的源极和漏极扩散区域的半导体衬底，源极和漏极扩散区域被器件沟道分离; 以及位于器件沟道顶部的栅极堆叠，栅极堆叠包括高k栅极电介质，绝缘中间层和完全硅化金属栅极导体，位于高k栅极电介质和完全硅化金属之间的绝缘中间层 栅极导体，其中所述绝缘中间层能够将所述半导体结构的阈值电压和平带电压稳定到目标值。

公开(公告)号：US08541275B2

公开(公告)日：2013-09-24

申请号：US12616941

申请日：2009-11-12

申请人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Matthew Copel

发明人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Matthew Copel

IPC分类号： H01L21/8238

CPC分类号： H01L21/3105 ,  H01L21/823842

摘要： A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer.

摘要翻译： 用于形成互补金属氧化物半导体器件的方法包括在电介质层上形成第一覆盖层，使用阻挡掩模阻挡覆盖层在要被保持的区域中的部分。 第一覆盖层的暴露部分与电介质层混合以形成第一混合层。 去除块掩模。 蚀刻第一覆盖层和第一混合层，使得除去第一覆盖层以在不去除第一混合层的情况下再次暴露在区域中的电介质层。

公开(公告)号：US20050266663A1

公开(公告)日：2005-12-01

申请号：US11174738

申请日：2005-07-06

申请人： Nestor Bojarczuk ,  Matthew Copel ,  Supratik Guha ,  Vijay Narayanan

发明人： Nestor Bojarczuk ,  Matthew Copel ,  Supratik Guha ,  Vijay Narayanan

IPC分类号： H01L21/20 ,  H01L21/316 ,  H01L21/36

CPC分类号： H01L21/02488 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/31604 ,  H01L21/31691 ,  Y10S438/967

摘要： A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD).

公开(公告)号：US20110108921A1

公开(公告)日：2011-05-12

申请号：US12616941

申请日：2009-11-12

申请人： SIVANANDA KANAKASABAPATHY ,  Hemanth Jagannathan ,  Matthew Copel

发明人： SIVANANDA KANAKASABAPATHY ,  Hemanth Jagannathan ,  Matthew Copel

IPC分类号： H01L27/092 ,  H01L21/306

CPC分类号： H01L21/3105 ,  H01L21/823842

摘要： A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer.

摘要翻译： 用于形成互补金属氧化物半导体器件的方法包括在电介质层上形成第一覆盖层，使用阻挡掩模阻挡覆盖层在要被保持的区域中的部分。 第一覆盖层的暴露部分与电介质层混合以形成第一混合层。 去除块掩模。 蚀刻第一覆盖层和第一混合层，使得除去第一覆盖层以在不去除第一混合层的情况下再次暴露在区域中的电介质层。

公开(公告)号：US20070099331A1

公开(公告)日：2007-05-03

申请号：US11506827

申请日：2006-08-21

申请人： David Mitzi ,  Matthew Copel

发明人： David Mitzi ,  Matthew Copel

IPC分类号： H01L21/00

CPC分类号： C23C18/1295 ,  C23C18/1204 ,  C23C18/1225 ,  C23C18/14 ,  H01L29/66742 ,  H01L29/78681 ,  Y10T428/25 ,  Y10T428/30 ,  Y10T428/31507 ,  Y10T428/31678

摘要： A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.

摘要翻译： 一种沉积金属硫族化物膜的方法，包括以下步骤：使金属硫族化物的分离的肼鎓前体与其中具有增溶添加剂的溶剂接触以形成其络合物溶液; 将复合物的溶液施加到基底上以在基底上产生溶液的涂层; 从涂层中除去溶剂以在基材上产生复合物的膜; 然后使复合物的膜退火，以在衬底上产生金属硫族化物膜。 还提供了制备金属硫族化物的分离的肼鎓前体的方法以及使用金属硫属元素作为沟道层的薄膜场效应晶体管器件。