公开(公告)号：US5418689A

公开(公告)日：1995-05-23

申请号：US12111

申请日：1993-02-01

申请人： Warren A. Alpaugh ,  Voya R. Markovich ,  Ajit K. Trivedi ,  Richard S. Zarr

发明人： Warren A. Alpaugh ,  Voya R. Markovich ,  Ajit K. Trivedi ,  Richard S. Zarr

IPC分类号： H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

CPC分类号： H05K1/112 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H05K3/4602 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15173 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/10674 ,  H05K2203/0207 ,  H05K2203/1394 ,  H05K2203/1581 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/4644 ,  H05K3/4652 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165

摘要： A printed circuit board or card for direct chip attachment that includes at least one power core, at least one signal plane that is adjacent to the power core, and plated through holes for electrical connection is provided. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer. Photodeveloped blind vias for subsequent connection to the power core and drilled blind vias for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.

摘要翻译： 提供了一种用于直接芯片附接的印刷电路板或卡，其包括至少一个电源核心，与功率核心相邻的至少一个信号平面以及用于电连接的电镀通孔。 此外，电介质材料层与功率芯相邻，并且电路化的导电层与电介质材料相邻，随后是与导电层相邻的一层光敏电介质材料。 提供用于随后连接到电源核心的盲孔和用于后续连接到信号平面的钻孔盲孔。 还提供了用于制造用于直接芯片附接的印刷电路板或卡的工艺。

公开(公告)号：US5316788A

公开(公告)日：1994-05-31

申请号：US736380

申请日：1991-07-26

申请人： Eric P. Dibble ,  Steven L. Hanakovic ,  Voya R. Markovich ,  Daniel S. Niedrich ,  Gary P. Vlasak ,  Richard S. Zarr ,  Richard C. Senger

发明人： Eric P. Dibble ,  Steven L. Hanakovic ,  Voya R. Markovich ,  Daniel S. Niedrich ,  Gary P. Vlasak ,  Richard S. Zarr ,  Richard C. Senger

IPC分类号： H01L21/52 ,  B23K1/00 ,  B23K1/08 ,  H01L21/48 ,  H01L21/60 ,  H01L23/498 ,  H05K3/06 ,  H05K3/18 ,  H05K3/24 ,  H05K3/34 ,  B05D1/00

CPC分类号： B23K1/085 ,  B23K1/0016 ,  H01L21/4853 ,  H01L23/49816 ,  H05K3/243 ,  H05K3/3468 ,  B23K2201/36 ,  H01L2924/0002 ,  H05K2201/0305 ,  H05K2203/043 ,  H05K2203/044 ,  H05K2203/054 ,  H05K3/067 ,  H05K3/3452

摘要： Process is described for applying large quantities of solder to small areas, such as the lands in a high density card, to which it is intended to surface mount electronic devices or directly attach circuitized chips. The land area is temporarily extended by depositing a relatively thin layer of metal beyond the perimeter of the land, wave soldering to deposit excess solder on the extended land region, and reflow, whereby the thin layer of metal dissolves into the solder, causing the solder to retract to the dimensions of the original land. Because the volume of solder is increased, the strength and reliability of the solder joint is greatly improved.

摘要翻译： 描述了用于将大量焊料应用于小面积，例如高密度卡片的焊盘，其旨在表面安装电子器件或直接附接电路化芯片。 通过在陆地周边沉积相对较薄的金属层，波峰焊接，将多余的焊料沉积在延伸的焊盘区域上，并回流焊接，由此金属薄层溶解到焊料中，引起焊料的临时扩展。 缩小到原始土地的尺寸。 因为焊料的体积增加，焊点的强度和可靠性大大提高。

公开(公告)号：US5597469A

公开(公告)日：1997-01-28

申请号：US387686

申请日：1995-02-13

申请人： Charles F. Carey ,  Kenneth M. Fallon ,  Voya R. Markovich ,  Douglas O. Powell ,  Gary P. Vlasak ,  Richard S. Zarr

发明人： Charles F. Carey ,  Kenneth M. Fallon ,  Voya R. Markovich ,  Douglas O. Powell ,  Gary P. Vlasak ,  Richard S. Zarr

IPC分类号： C25D5/02 ,  C25D5/08 ,  H01L21/48 ,  H01L21/60 ,  H05K3/24 ,  H05K3/34

CPC分类号： H01L24/81 ,  C25D5/022 ,  C25D5/08 ,  H01L21/4825 ,  H01L21/4853 ,  H05K3/241 ,  H05K3/3473 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H05K2203/043 ,  H05K2203/054

摘要： Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.

摘要翻译： 可以通过在具有孔或凹槽（例如盲孔）的电介质层的表面上沉积导电材料层并且暴露于其中的导体和/或焊盘而形成具有高体积精度和形状均匀性的小的，紧密间隔的焊料材料沉积物 孔或凹槽，导电材料的掩模区域和另外的图案化介电层，将电镀焊料材料电镀到由掩模曝光的导电材料的区域上，通过选择性蚀刻和至少从至少 有孔电介质层的一部分表面。 盲孔内电镀的均匀性通过流体喷射和阴极搅拌的组合增强。 在电镀之前，可以通过在浸没池中用焊料材料的构成成分代替导体材料来避免所得到的焊料沉积物中的过多的导体材料。

公开(公告)号：US4820643A

公开(公告)日：1989-04-11

申请号：US161233

申请日：1988-02-17

申请人： William J. Amelio ,  Kenneth R. Czarnecki ,  Gary K. Lemon ,  Voya Markovich ,  Carlos J. Sambucetti ,  Richard S. Zarr

发明人： William J. Amelio ,  Kenneth R. Czarnecki ,  Gary K. Lemon ,  Voya Markovich ,  Carlos J. Sambucetti ,  Richard S. Zarr

IPC分类号： G01N27/48 ,  G01N21/00 ,  G01N33/20

CPC分类号： G01N27/48

摘要： The effectiveness of a palladium-tin catalyst for subsequent plating thereon is determined by employing cyclic voltammetry.

摘要翻译： 通过使用循环伏安法测定钯 - 锡催化剂随后电镀的效果。