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公开(公告)号：US06580650B2
公开(公告)日：2003-06-17
申请号：US09810325
申请日：2001-03-16
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C8/08
摘要： A DC analog circuit which monitors a DRAM sample cell access device and outputs a DC reference voltage to the word line voltage regulation system. The resulting output voltage Vpp from the word line voltage regulation system will then vary in accordance with the cell access device parametrics so as to guarantee a full high level will always be written into the DRAM cell.
摘要翻译： DC模拟电路，用于监视DRAM采样单元存取装置，并将直流参考电压输出到字线电压调节系统。 然后，来自字线电压调节系统的结果输出电压Vpp将根据信元接入设备参数而变化，以保证将始终向DRAM单元写入一个完整的高电平。
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公开(公告)号：US6121106A
公开(公告)日：2000-09-19
申请号：US38395
申请日：1998-03-11
IPC分类号： H01L21/334 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10894 , H01L29/66181
摘要： A shallow trench capacitor is disclosed that is fabricated by forming a shallow trench in a substrate extending below a surface of the substrate. A dielectric layer having a preselected thickness is grown in the shallow trench, and a polysilicon layer is deposited over the dielectric layer. The polysilicon layer is then planarized down to the nitride or pad layer forming a capacitor. By utilizing a non-critical mask to open up selected regions, isolation structures may then be formed through shallow trench technology.
摘要翻译： 公开了一种浅沟槽电容器，其通过在衬底的表面下方延伸的衬底中形成浅沟槽来制造。 在浅沟槽中生长具有预选厚度的电介质层，并且在电介质层上沉积多晶硅层。 然后将多晶硅层平坦化成形成电容器的氮化物或焊盘层。 通过利用非关键掩模来打开所选择的区域，然后可以通过浅沟槽技术形成隔离结构。
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公开(公告)号：US06399990B1
公开(公告)日：2002-06-04
申请号：US09531362
申请日：2000-03-21
IPC分类号： H01L2972
CPC分类号： H01L27/0266
摘要： The present invention relates generally to protection of integrated circuits from electrostatic discharges and more specifically to the use of devices formed in isolated well regions for electrostatic discharge protection. One aspect of the present invention is an ESD protection circuit that includes a first FET and a second FET. The drain of the first FET is coupled to an ESD susceptible node and the source of the first FET is coupled to a first voltage terminal. The gate and a well of the first FET are coupled together and to the drain of the second FET. The source of the second FET is coupled to the first voltage terminal. The gate of the second FET is coupled to a second voltage terminal. The second voltage terminal is connected to a voltage source that is at the first voltage when the circuit is not powered, and at a voltage above the threshold voltage of the second FET when the circuit is powered. The well in which the first FET is formed is electrically isolated from other wells in the substrate. The electrical isolation surrounding the well includes (1) a second-type dopant isolation regions in a first type substrate surrounding and abutting the well, (2) a substrate doped with second type doping, and (3) dielectric isolation, such as deep trench, STI, and buried oxide layer. The well may be isolated by any of these methods separately or in combination.
摘要翻译： 本发明一般涉及集成电路与静电放电的保护，更具体地涉及在隔离阱区域中形成的用于静电放电保护的器件的使用。 本发明的一个方面是包括第一FET和第二FET的ESD保护电路。 第一FET的漏极耦合到ESD敏感节点，并且第一FET的源极耦合到第一电压端子。 第一FET的栅极和阱耦合在一起并连接到第二FET的漏极。 第二FET的源极耦合到第一电压端子。 第二FET的栅极耦合到第二电压端子。 当电路未通电时，第二电压端子连接到处于第一电压的电压源，并且当电路通电时，电压高于第二FET的阈值电压。 其中形成第一FET的阱与衬底中的其它阱电隔离。 围绕阱的电隔离包括（1）围绕和邻接阱的第一类型衬底中的第二类型掺杂剂隔离区，（2）掺杂有第二类掺杂的衬底，以及（3）电介质隔离，例如深沟槽 ，STI和埋氧层。 可以通过任何这些方法单独或组合地分离井。
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公开(公告)号：US06437385B1
公开(公告)日：2002-08-20
申请号：US09607094
申请日：2000-06-29
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10832 , H01L28/55 , H01L28/87 , H01L29/66181 , H01L29/945
摘要： Use of different materials for different conductive films forming plates or electrodes of one or more capacitors formed in a trench in a body of semiconductor materials allow connections to be made selectively to the plates. The films may be undercut by different etchants at respective connection apertures to avoid formation of connections or connections made by doped polysilicon of different conductivities forming connections to some plates of similarly doped polysilicon and blocking diode junctions with oppositely doped polysilicon. The blocking diodes may include a compensation implant to adjust reverse breakdown characteristics and provide transient and electrostatic discharge protection.
摘要翻译： 对于形成在半导体材料体中的沟槽中的一个或多个电容器形成板或不同导电膜的不同材料的使用允许选择性地连接板。 这些膜可能在相应的连接孔处被不同的蚀刻剂削弱，以避免由不同导电性的掺杂多晶硅形成的连接或连接形成连接到具有相反掺杂多晶硅的类似掺杂多晶硅和阻塞二极管结的某些平板。 阻塞二极管可以包括补偿注入以调整反向击穿特性并提供瞬态和静电放电保护。
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公开(公告)号：US06369671B1
公开(公告)日：2002-04-09
申请号：US09281412
申请日：1999-03-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01P1185
CPC分类号： G11C7/12
摘要： A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.
摘要翻译： 一种具有衬底的半导体结构，在衬底的一部分上方的绝缘体，绝缘体上方的导体; 以及在所述衬底的所述部分的相对侧上的所述衬底中的至少两个接触区域，其中所述接触区域之间的电压调制所述导体的电容。
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公开(公告)号：US06255899B1
公开(公告)日：2001-07-03
申请号：US09388164
申请日：1999-09-01
申请人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2500
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06517 , H01L2225/0652 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/16152 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： An assembly is provided that includes an interposer having first and second substantially flat, opposed surfaces, and at least one speed critical signal line extending directly through the interposer from the first surface to the second surface. A first IC is coupled to the first surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. A second IC is coupled to the second surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. Preferably at least one non-speed critical signal line is provided within the interposer and is coupled to a second external connection mechanism of the first IC and/or the second IC for delivering non-speed critical signals thereto or for receiving such signals therefrom. A chip carrier having a cavity formed therein also may be provided wherein the second surface of the interposer is coupled to the chip carrier and the second IC is disposed within the cavity. One or more carrier signal lines may be provided within the chip carrier and coupled between the interposer and the second IC. The first and/or the second IC also may comprise control logic adapted to select a number of drivers within either IC that drive a particular signal line.
摘要翻译： 提供了一种组件，其包括具有第一和第二基本上平坦的相对表面的插入件以及至少一个直线从第一表面延伸到第二表面的速度临界信号线。 第一IC耦合到插入器的第一表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。 第二IC耦合到插入器的第二表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。 优选地，在插入器内提供至少一个非速度临界信号线，并且耦合到第一IC和/或第二IC的第二外部连接机构，用于向其递送非速度关键信号或用于从其接收这样的信号。 还可以提供其中形成有空腔的芯片载体，其中插入器的第二表面耦合到芯片载体，并且第二IC设置在空腔内。 可以在芯片载体内提供一个或多个载波信号线，并且耦合在插入器和第二IC之间。 第一和/或第二IC还可以包括适于选择驱动特定信号线的IC内的多个驱动器的控制逻辑。
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公开(公告)号：US06177818B1
公开(公告)日：2001-01-23
申请号：US09303508
申请日：1999-04-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , William R. Tonti
IPC分类号： H03B2100
CPC分类号： H03K19/09482 , H03K19/00361 , H03K19/018521
摘要： An off-chip driver circuit including an enhancement PFET, a depletion PFET, a depletion NFET and an enhancement NFET connected in series. The large enhancement PFET and large enhancement NFET turn off the OCD in tri-state and to turn off the unused half of the OCD to prevent overlap current when driving a ‘0’ or a ‘1’. A first gate signal is applied to the gate of the enhancement PFET and a second gate signal is applied to the enhancement NFET. A fixed voltage is connected to the gate of the depletion NFET and ground to gate of the depletion PFET. An output signal is obtained from a node between the depletion PFET and depletion NFET devices. In another embodiment, a reflection/overshoot sensor 60 is added. The output of sensor is connected to the body of a depletion PFET and an NFET. The feedback from sensor is such that the threshold voltage of the depletion devices are made more positive if the sensor detects that the output is being over-driven. A more positive threshold voltage will reduce the driver's IDS, but leaves the device in the linear mode.
摘要翻译： 包括增强型PFET，耗尽型PFET，耗尽型NFET和增强型NFET的片外驱动电路。 大增强型PFET和大增强型NFET在三态关闭OCD并关闭OCD的未使用的一半以防止在驱动“0”或“1”时重叠电流。 第一栅极信号被施加到增强PFET的栅极，并且第二栅极信号被施加到增强NFET。 固定电压连接到耗尽型NFET的栅极，并连接到耗尽PFET的栅极。 从耗尽PFET和耗尽NFET器件之间的节点获得输出信号。 在另一个实施例中，添加了反射/过冲传感器60。 传感器的输出连接到耗尽PFET和NFET的主体。 来自传感器的反馈使得如果传感器检测到输出被过驱动，则耗尽装置的阈值电压变得更为正。 更正的阈值电压将减少驾驶员的IDS，但使设备处于线性模式。
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公开(公告)号：US06496037B1
公开(公告)日：2002-12-17
申请号：US09588202
申请日：2000-06-06
IPC分类号： H03K190175
CPC分类号： H03K19/0005
摘要： An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.
摘要翻译： 提供了一种自动驱动器调节器及其使用方法，其基于负载特性修改片外驱动器。 优选的实施方案优选是自动的，并且需要很少的或不需要人为干预。 本发明的优选实施例分析和确定节点的阻抗并且响应于节点的阻抗调整输出驱动器的数量，或者分析由输入波形引起的节点的合成波形，并且调整多个 输出驱动器响应于该结点的合成波形。
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公开(公告)号：US07098083B2
公开(公告)日：2006-08-29
申请号：US10652534
申请日：2003-08-29
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.
摘要翻译： 一种可编程元件，其具有第一二极管，其具有电极和设置在所述基板和所述第一器件的所述电极之间的第一绝缘体，所述第一绝缘体具有给定特性的第一值，以及设置有电极和第二绝缘体的FET 在所述基板和所述第二装置的所述电极之间，所述第二绝缘体具有与所述第一值不同的所述给定特性的第二值。 二极管和FET的电极彼此耦合，并且编程能量源耦合到二极管，以使其在编程时永久地降低电阻率。 二极管的编程状态由FET中的电流表示，该电流由读出锁存器读取。 因此，二极管中的小电阻变化转换为锁存器中的大信号增益/变化。 这允许二极管在较低的电压下被编程。
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10.发明授权公开(公告)号：US06222395B1
公开(公告)日：2001-04-24
申请号：US09225112
申请日：1999-01-04
IPC分类号： G05F110
CPC分类号： G05F3/205
摘要： A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.
摘要翻译： 一种差分接收器，用于通过使用通过差分对间隔晶体管之间的阈值电压差而获得的内置参考电压来感测小输入电压摆幅。 阈值电压的差异可以通过使用相同材料的晶体管对的栅极的离子注入的不同值，或通过使用不同材料的剂量来产生。 也可以通过使用不同的晶体管沟道长度来获得阈值电压的差异。 也可以通过使用电压控制衬底装置控制晶体管衬底电压来调制阈值电压。
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