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    METHOD FOR MANUFACTURING THROUGH-SILICON VIA
    2.
    发明申请
    METHOD FOR MANUFACTURING THROUGH-SILICON VIA 有权
    通过硅制造方法

    公开(公告)号：US20120142190A1

    公开(公告)日：2012-06-07

    申请号：US12962055

    申请日：2010-12-07

    Applicant: Wei-Che TSAO ,  Wen-Chin Lin

    Inventor： Wei-Che TSAO ,  Wen-Chin Lin

    IPC: H01L21/306

    CPC classification number: H01L21/76898 ,  H01L21/7684

    Abstract: A method for manufacturing TSVs comprises following steps: A stack structure having a substrate, an ILD layer and a dielectric stop layer is provided, in which an opening penetrating through the ILD layer and the dialectic stop layer and further extending into the substrate is formed. After an insulator layer and a metal barrier are formed on the stack structure, a top metal layer is formed on the stack structure to fulfill the opening. A first planarization process stopping on the metal barrier is conducted, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer. A second planarization process stopping on the dielectric stop layer is conducted, wherein the second planarization process has a polishing rate for removing the insulator layer greater than that for removing the dielectric stop layer. The dielectric stop layer is than removed.

    Abstract translation: 制造TSV的方法包括以下步骤：提供具有基板，ILD层和电介质停止层的堆叠结构，其中形成穿透ILD层和辩证阻止层并进一步延伸到基板中的开口。 在堆叠结构上形成绝缘体层和金属屏障之后，在堆叠结构上形成顶部金属层以实现开口。 进行停止在金属屏障上的第一平面化处理，其中第一平面化工艺具有除去金属屏障的抛光速率小于除去顶部金属层的抛光速率。 进行停止在电介质停止层上的第二平坦化工艺，其中第二平坦化工艺具有用于除去绝缘体层的抛光速率大于去除电介质停止层的抛光速率。 电介质停止层除去。

    Cleaning Method for Wafer
    3.
    发明申请
    Cleaning Method for Wafer 审中-公开
    晶圆清洗方法

    公开(公告)号：US20120048296A1

    公开(公告)日：2012-03-01

    申请号：US12868726

    申请日：2010-08-26

    Applicant: Wen-Chin Lin ,  Kai-Chun Yang ,  Jen-Chieh Lin ,  Jeng-Yu Fang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Wei-Che Tsao

    Inventor： Wen-Chin Lin ,  Kai-Chun Yang ,  Jen-Chieh Lin ,  Jeng-Yu Fang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Wei-Che Tsao

    IPC: B08B7/00 ,  B08B3/00

    CPC classification number: C11D11/0047 ,  C11D11/0064 ,  H01L21/02074

    Abstract: A cleaning method for a wafer is provided. First, a first cleaning process is performed wherein the first cleaning process includes providing a cleaning solution having a first concentration. Next, a second cleaning process is performed, wherein the second cleaning process includes providing the cleaning solution having a second concentration. The second concentration is substantially greater than the first concentration. Next, a post-cleaning process is performed to provide dilute water.

    Abstract translation: 提供了一种用于晶片的清洁方法。 首先，进行第一清洗处理，其中第一清洗过程包括提供具有第一浓度的清洗溶液。 接下来，执行第二清洁处理，其中第二清洁处理包括提供具有第二浓度的清洁溶液。 第二浓度显着大于第一浓度。 接下来，进行后清洗处理以提供稀释水。

    Method for manufacturing through-silicon via
    4.
    发明授权
    Method for manufacturing through-silicon via 有权
    硅通孔制造方法

    公开(公告)号：US08367553B2

    公开(公告)日：2013-02-05

    申请号：US12962055

    申请日：2010-12-07

    Applicant: Wei-Che Tsao ,  Wen-Chin Lin

    Inventor： Wei-Che Tsao ,  Wen-Chin Lin

    IPC: H01L21/306

    CPC classification number: H01L21/76898 ,  H01L21/7684

    Abstract: A method for manufacturing TSVs comprises following steps: A stack structure having a substrate, an ILD layer and a dielectric stop layer is provided, in which an opening penetrating through the ILD layer and the dialectic stop layer and further extending into the substrate is formed. After an insulator layer and a metal barrier are formed on the stack structure, a top metal layer is formed on the stack structure to fulfill the opening. A first planarization process stopping on the metal barrier is conducted, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer. A second planarization process stopping on the dielectric stop layer is conducted, wherein the second planarization process has a polishing rate for removing the insulator layer greater than that for removing the dielectric stop layer. The dielectric stop layer is than removed.

    Abstract translation: 制造TSV的方法包括以下步骤：提供具有基板，ILD层和电介质停止层的堆叠结构，其中形成穿透ILD层和辩证阻止层并进一步延伸到基板中的开口。 在堆叠结构上形成绝缘体层和金属屏障之后，在堆叠结构上形成顶部金属层以实现开口。 进行停止在金属屏障上的第一平面化处理，其中第一平面化工艺具有除去金属屏障的抛光速率小于除去顶部金属层的抛光速率。 进行停止在电介质停止层上的第二平坦化工艺，其中第二平坦化工艺具有用于除去绝缘体层的抛光速率大于去除电介质停止层的抛光速率。 电介质停止层除去。

    METHOD FOR MANUFACTURING THROUGH-SILICON VIA
    5.
    发明申请
    METHOD FOR MANUFACTURING THROUGH-SILICON VIA 有权
    通过硅制造方法

    公开(公告)号：US20130011938A1

    公开(公告)日：2013-01-10

    申请号：US13176790

    申请日：2011-07-06

    Applicant: Wei-Che TSAO ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

    Inventor： Wei-Che TSAO ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

    IPC: H01L21/66 ,  H01L21/306 ,  H01L21/304

    CPC classification number: H01L21/31053 ,  H01L21/3212 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

    Abstract translation: 一种制造TSV的方法，其中该方法包括以下几个步骤：提供具有基板和ILD层（层间电介质层）的堆叠结构，其中穿透ILD层并进一步延伸到基板中的开口是 形成。 在堆叠结构和开口的侧壁上形成绝缘体层和金属阻挡层之后，在堆叠结构上形成顶部金属层以实现开口。 进行停止在阻挡层上的第一平面化处理以去除顶部金属层的一部分。 随后进行停止在ILD层上的第二平坦化处理以去除金属阻挡层的一部分，绝缘体层的一部分和顶部金属层的一部分，其中第二平坦化工艺具有由光线确定的抛光终点 干涉测量或电机电流。

    Method for forming a reduced active area in a phase change memory structure
    8.
    发明授权
    Method for forming a reduced active area in a phase change memory structure 有权
    在相变存储器结构中形成减小的有效面积的方法

    公开(公告)号：US08153471B2

    公开(公告)日：2012-04-10

    申请号：US12945860

    申请日：2010-11-14

    Applicant: Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

    Inventor： Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

    IPC: H01L21/06

    CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1691

    Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.

    Abstract translation: 一种相变存储器结构及其形成方法，所述方法包括提供包括导电区域的衬底; 在间隔物的上部形成具有部分暴露的侧壁区域的间隔物，其限定相变存储元件接触区域; 并且其中所述间隔件底部部分与所述导电区域重叠。 这两种方法都可以减少相变存储元件的有效面积，从而减少所需的相变电流。

    Semiconductor device with semi-insulating substrate portions
    9.
    发明授权
    Semiconductor device with semi-insulating substrate portions 有权
    具有半绝缘衬底部分的半导体器件

    公开(公告)号：US07964900B2

    公开(公告)日：2011-06-21

    申请号：US12586688

    申请日：2009-09-24

    Applicant: Wen-Chin Lin ,  Denny Tang ,  Chuan-Ying Lee ,  Hsu Chen Cheng

    Inventor： Wen-Chin Lin ,  Denny Tang ,  Chuan-Ying Lee ,  Hsu Chen Cheng

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L21/76 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/08

    Abstract: A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.

    Abstract translation: 半导体衬底包括在半导体子结构上形成的图案化硬掩模膜的开口下方的半绝缘部分，其厚度足以防止带电粒子通过硬掩模。 半绝缘部分包括带电粒子并且可以深深地延伸到半导体衬底中并且电绝缘形成在半绝缘部分的相对侧上的器件。 带电粒子可以有利地是质子，并且由图案化的硬掩模膜覆盖的另外的基底部分基本上没有带电粒子。

    Magnetic memory cells and manufacturing methods
    10.
    发明授权
    Magnetic memory cells and manufacturing methods 有权
    磁记忆体和制造方法

    公开(公告)号：US07554145B2

    公开(公告)日：2009-06-30

    申请号：US11610760

    申请日：2006-12-14

    Applicant: Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    Inventor： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    IPC: H01L29/76

    CPC classification number: H01L43/12 ,  H01L27/228

    Abstract: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

    Abstract translation: 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。

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