公开(公告)号：US20160315009A1

公开(公告)日：2016-10-27

申请号：US14697391

申请日：2015-04-27

申请人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

IPC分类号： H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/67 ,  H01L21/308 ,  H01L21/3065

CPC分类号： H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，在半导体晶片的正面上切割具有多个集成电路的半导体晶片的方法包括将半导体晶片的背面粘附在基板载体的切割带上。 在将半导体晶片粘附在切割带上之后，用UV固化工艺处理切割带。 在通过UV固化处理处理切割带之后，在半导体晶片的前侧形成切割掩模，该切割掩模覆盖并保护集成电路。 用激光刻划工艺对切割掩模进行图案化，以在切割掩模之间提供间隙，在半导体晶片的间隙暴露在集成电路之间。 通过切割掩模层中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US09355907B1

公开(公告)日：2016-05-31

申请号：US14589918

申请日：2015-01-05

申请人： Wei-Sheng Lei ,  Jungrae Park ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Wei-Sheng Lei ,  Jungrae Park ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/78 ,  H01L23/28 ,  H01L21/82 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/02 ,  H01L21/67 ,  H01J37/32

CPC分类号： H01L21/82 ,  B23K26/364 ,  B23K2103/56 ,  H01J37/32889 ,  H01J37/32899 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/02057 ,  H01L21/02076 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/67207 ,  H01L21/78

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a line shaped laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。 然后用线形激光束轮廓激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US09601375B2

公开(公告)日：2017-03-21

申请号：US14697391

申请日：2015-04-27

申请人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

IPC分类号： H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L21/447 ,  H01L21/48 ,  H01L21/50 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/268 ,  H01L21/67 ,  H01L21/683

CPC分类号： H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.

公开(公告)号：US20150221505A1

公开(公告)日：2015-08-06

申请号：US14658102

申请日：2015-03-13

申请人： Jungrae Park ,  Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Jungrae Park ,  Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/02 ,  H01L21/683 ,  H01L21/308 ,  B05B3/10 ,  B05B1/00

CPC分类号： H01L21/02282 ,  B05B1/00 ,  B05B3/1014 ,  B05B3/1035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6715 ,  H01L21/6835 ,  H01L21/78 ,  H01L2221/68327

摘要： Improved wafer coating processes, apparatuses, and systems are described. In one embodiment, an improved spin-coating process and system is used to form a mask for dicing a semiconductor wafer with a laser plasma dicing process. In one embodiment, a spin-coating apparatus for forming a film over a semiconductor wafer includes a rotatable stage configured to support the semiconductor wafer. The rotatable stage has a downward sloping region positioned beyond a perimeter of the semiconductor wafer. The apparatus includes a nozzle positioned above the rotatable stage and configured to dispense a liquid over the semiconductor wafer. The apparatus also includes a motor configured to rotate the rotatable stage.

摘要翻译： 描述了改进的晶片涂布工艺，装置和系统。 在一个实施例中，改进的旋涂工艺和系统用于形成用激光等离子体切割工艺切割半导体晶片的掩模。 在一个实施例中，用于在半导体晶片上形成膜的旋涂装置包括被配置为支撑半导体晶片的可旋转台。 可旋转台具有位于半导体晶片周边之外的向下倾斜区域。 该设备包括位于可旋转台上方并被配置为在半导体晶片上分配液体的喷嘴。 该装置还包括构造成旋转可旋转台的马达。

公开(公告)号：US09196536B1

公开(公告)日：2015-11-24

申请号：US14497027

申请日：2014-09-25

申请人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/82 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/67 ,  H01J37/32 ,  B23K26/40 ,  B23K26/36

CPC分类号： H01L21/3065 ,  H01J37/32 ,  H01J37/32889 ,  H01J37/32899 ,  H01J37/32926 ,  H01J2237/2487 ,  H01J2237/334 ,  H01J2237/3341 ,  H01J2237/335 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67115 ,  H01L21/78

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a phase modulated laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。 然后用相位调制的激光束轮廓激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US20150243559A1

公开(公告)日：2015-08-27

申请号：US14265139

申请日：2014-04-29

申请人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/78 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/308

CPC分类号： H01L21/78 ,  B23K26/0624 ,  B23K26/0661 ,  B23K26/18 ,  B23K26/364 ,  B23K2101/40 ,  B23K2103/166 ,  B23K2103/50 ,  B23K2103/56 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32135

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a temporally-controlled laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The temporally-controlled laser scribing process involves scribing with a laser beam having a profile comprising a leading femto-second portion and a trailing lower-intensity, higher fluence portion. The method also involves plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 该方法还包括用时间控制的激光划线工艺对掩模进行图案化，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 时间控制的激光划线方法包括用具有包括前导毫微微秒部分和尾随较低强度，较高注量部分的轮廓的激光束划线。 该方法还包括通过图案化掩模中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。

公开(公告)号：US09281244B1

公开(公告)日：2016-03-08

申请号：US14490598

申请日：2014-09-18

申请人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/02 ,  H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/67 ,  H01J37/32 ,  B23K26/36

CPC分类号： H01L21/78 ,  B23K26/364 ,  H01J37/32889 ,  H01J2237/335 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/67207

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an adaptive optics-controlled laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。 然后用自适应光学控制激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US09177861B1

公开(公告)日：2015-11-03

申请号：US14491728

申请日：2014-09-19

申请人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/00 ,  H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/67 ,  H01J37/32 ,  B23K26/36 ,  B23K26/16

CPC分类号： H01L21/3065 ,  B23K26/0736 ,  B23K26/367 ,  B23K26/38 ,  B23K2103/56 ,  H01J37/32 ,  H01J37/32889 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/78

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an elliptical or a spatio-temporal controlled laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。 然后用椭圆形或空间 - 时间控制的激光束轮廓激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US20150214109A1

公开(公告)日：2015-07-30

申请号：US14167300

申请日：2014-01-29

申请人： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar ,  James S. Papanu ,  Jungrae Park

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar ,  James S. Papanu ,  Jungrae Park

IPC分类号： H01L21/78 ,  H01J37/32 ,  H01L21/67 ,  H01L21/308 ,  H01L21/3065

CPC分类号： H01L21/78 ,  B23K26/361 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31127 ,  H01L21/67207

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is exposed to a plasma treatment process to increase an etch resistance of the mask. The mask is patterned with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to exposing the mask to the plasma treatment process, the semiconductor wafer is plasma etched through the gaps in the mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 将掩模暴露于等离子体处理工艺以增加掩模的耐蚀刻性。 用激光划线工艺对掩模进行图案化，以在掩模中提供间隙，使间隙暴露集成电路之间的半导体晶片的区域。 在将掩模暴露于等离子体处理工艺之后，通过掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US20170256500A1

公开(公告)日：2017-09-07

申请号：US15060224

申请日：2016-03-03

申请人： Jungrae Park ,  Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

发明人： Jungrae Park ,  Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

IPC分类号： H01L23/544 ,  B23K10/00 ,  B23K26/0622 ,  H01L21/78

CPC分类号： H01L23/544 ,  A47G19/22 ,  A47G19/2272 ,  B23K10/003 ,  B23K26/0624 ,  B65D47/244 ,  B65D47/32 ,  H01L21/78 ,  H01L2223/5446

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.