公开(公告)号：US20090053872A1

公开(公告)日：2009-02-26

申请号：US12282300

申请日：2007-03-09

申请人： Wibo D. Van Noort ,  Jan Sonsky ,  Andreas M. Piontek

发明人： Wibo D. Van Noort ,  Jan Sonsky ,  Andreas M. Piontek

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7371

摘要： The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate (11) which is provided with a first, a second and a third layer (1,2,3) of a first, second and third semiconductor material respectively, all of a first conductivity type. A first portion of the second layer (2) is transformed into a buried isolation region (15) comprising a first electrically insulating material. A first semiconductor region (6) of the first conductivity type, comprising, for example, a collector region, is formed from a second portion of the second layer (2) adjoining the buried isolation region (15) and a portion of the first layer (1) adjoining the second portion of the second layer (2). Then a base region (7) is formed on the buried isolation region (15) and on the first semiconductor region (6) by transforming the third layer (3) into a second conductivity type, which is opposite to the first conductivity type. Thereafter a second semiconductor region (8) of the first conductivity type, comprising, for example, an emitter region, is formed on a part of the base region (7). This method provides for the formation of a bipolar transistor with an advantageous decrease of the extrinsic collector to base region (6,7) capacitance by the fact that the value of this capacitance is mainly determined by the buried isolation region (15) which has a substantially lower dielectric constant than that of the collector to base region (6,7) junction.

摘要翻译： 本发明涉及在半导体衬底（11）上制造双极晶体管的方法，该半导体衬底分别具有第一，第二和第三半导体材料的第一，第二和第三层（1,2,3），全部 的第一导电类型。 第二层（2）的第一部分被转换成包括第一电绝缘材料的掩埋隔离区（15）。 第一导电类型的第一半导体区域（6）由包括例如集电极区域的第一半导体区域（6）由毗邻掩埋隔离区域（15）的第二层（2）的第二部分和第一层 （1）邻接第二层（2）的第二部分。 然后，通过将第三层（3）转变成与第一导电类型相反的第二导电类型，在掩埋隔离区（15）和第一半导体区（6）上形成基极区（7）。 此后，在基极区域（7）的一部分上形成第一导电类型的第二半导体区域（8），其包括例如发射极区域。 该方法通过以下事实来形成双极性晶体管，该双极晶体管有利于减少外部集电极到基极区域（6,7）的电容，该电容值主要由埋入隔离区域（15）确定， 比集电极到基极区（6,7）结的介电常数要低得多。

公开(公告)号：US20100237434A1

公开(公告)日：2010-09-23

申请号：US11993296

申请日：2006-06-22

申请人： Wibo D. Van Noort ,  Jan Sonsky ,  Philippe Meunier-Beillard ,  Erwin Hijzen

发明人： Wibo D. Van Noort ,  Jan Sonsky ,  Philippe Meunier-Beillard ,  Erwin Hijzen

IPC分类号： H01L27/06 ,  H01L29/68 ,  H01L21/70

CPC分类号： H01L29/7378 ,  B82Y20/00 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/1087 ,  H01L29/41708 ,  H01L29/42384 ,  H01L29/66242 ,  H01L29/78 ,  H01L29/78645 ,  H01L29/78696 ,  H01L31/035236 ,  H01L31/1812 ,  Y02E10/50

摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention. Such a buried low resistance offers substantial advantages both for a bipolar transistor and for a MOS transistor.

摘要翻译： 本发明涉及具有衬底（11）和硅的半导体本体（12）的半导体器件（10），其包括具有晶体管（T）的有源区（A）和围绕有源区的无源区（P） （A），并且设置有金属材料的埋入导电区域（1），所述埋入导电区域连接到从所述半导体主体（12）的表面凹陷的金属材料的导电区域（2），所述埋入导电区域 区域（1）在半导体本体（12）的表面处可电连接。 根据本发明，在半导体本体（12）的有源区（A）的位置处形成掩埋导电区（1）。 以这种方式，可以使用与周围的硅具有完全不同的晶体学特性的金属材料，在半导体本体（12）的有源区（A）中局部地产生非常低的掩埋电阻。 这可以通过使用根据本发明的方法来实现。 这种埋下的低电阻为双极晶体管和MOS晶体管提供了显着的优点。

公开(公告)号：US07923345B2

公开(公告)日：2011-04-12

申请号：US12158988

申请日：2006-12-18

申请人： Jan Sonsky ,  Wibo D. Van Noort

发明人： Jan Sonsky ,  Wibo D. Van Noort

IPC分类号： H01L21/76 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76229 ,  B81C1/00158 ,  B81C2201/014

摘要： A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.

摘要翻译： 一种制造半导体器件的方法，其中包括牺牲层的层压结构被夹在两个蚀刻停止层（8,11）之间，并且将半导体膜（9）与体基板（1）分离，以提供未刻划的结构 。 通过半导体层（9）的厚度和通过上蚀刻停止层（8）在层状结构中形成通路沟槽（4）和支撑沟槽（5）。 支撑沟槽通过牺牲层（12）和下蚀刻停止层更深地延伸并被填充。 牺牲层被暴露并被选择性地蚀刻到蚀刻停止层以形成空腔（30）并且实现通过包括填充的支撑沟槽的垂直支撑结构附接到主体衬底的半导体膜。

公开(公告)号：US20090227091A1

公开(公告)日：2009-09-10

申请号：US12158988

申请日：2006-12-18

申请人： Jan Sonsky ,  Wibo D. Van Noort

发明人： Jan Sonsky ,  Wibo D. Van Noort

IPC分类号： H01L21/20

CPC分类号： H01L21/76229 ,  B81C1/00158 ,  B81C2201/014

摘要： A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.

摘要翻译： 一种制造半导体器件的方法，其中包括牺牲层的层压结构被夹在两个蚀刻停止层（8,11）之间，并且将半导体膜（9）与体基板（1）分离，以提供未刻划的结构 。 通过半导体层（9）的厚度和通过上蚀刻停止层（8）在层状结构中形成通路沟槽（4）和支撑沟槽（5）。 支撑沟槽通过牺牲层（12）和下蚀刻停止层更深地延伸并被填充。 牺牲层被暴露并被选择性地蚀刻到蚀刻停止层以形成空腔（30）并且实现通过包括填充的支撑沟槽的垂直支撑结构附接到主体衬底的半导体膜。

公开(公告)号：US20110101452A1

公开(公告)日：2011-05-05

申请号：US12995083

申请日：2009-05-20

申请人： Jan Sonsky ,  Eero Saarnilehto

发明人： Jan Sonsky ,  Eero Saarnilehto

IPC分类号： H01L29/78 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L21/3247 ,  H01L21/74 ,  H01L21/743 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7812

摘要： A trench-gate semiconductor device configuration is provided which is suitable for incorporation in integrated circuits, together with methods for its manufacture. A self-aligned drain region (12a) is provided below the device trench (18). The manufacturing methods include etching an initial trench into a semiconductor body (8), and annealing so as to cause migration of material such that a shallower trench with a cavity (36) below it are formed. The drain region is then formed in the cavity.

摘要翻译： 提供了一种适合于集成在集成电路中的沟槽栅半导体器件结构及其制造方法。 在器件沟槽（18）的下方提供自对齐漏极区（12a）。 制造方法包括将初始沟槽蚀刻到半导体本体（8）中，并退火以引起材料的迁移，使得形成具有在其下方的空腔（36）的较浅的沟槽。 然后在空腔中形成漏极区。

公开(公告)号：US20080296694A1

公开(公告)日：2008-12-04

申请号：US12158136

申请日：2006-12-18

申请人： Jan Sonsky

发明人： Jan Sonsky

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/66659 ,  H01L27/0617 ,  H01L29/0653 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/786

摘要： A method of making a semiconductor device includes forming shallow trench isolation structures (14) in a semiconductor device layer. The shallow trench isolation structures are U- or O-shaped enclosing field regions (28) formed of the semiconductor device layer which is doped and/or suicided to be conducting. The semiconductor device may include an extended drain region (50) or drift region and a drain region (42). An insulated gate (26) may be provided over the body region. A source region (34, 40) may be shaped to have a deep source region (40) and a shallow source region (34). A contact region (60) of the same conductivity type as the body may be provided adjacent to the deep source region (40). The body extends under the shallow source region (34) to contact the contact region (60).

摘要翻译： 制造半导体器件的方法包括在半导体器件层中形成浅沟槽隔离结构（14）。 浅沟槽隔离结构是由半导体器件层形成的U形或O形包围场区（28），其被掺杂和/或被自动导电。 半导体器件可以包括延伸的漏极区（50）或漂移区和漏极区（42）。 可以在身体区域上设置绝缘门（26）。 源区域（34,40）可以被成形为具有深源区（40）和浅源区（34）。 与深源区（40）相邻可以设置与主体相同导电类型的接触区（60）。 主体延伸在浅源区（34）下方以接触接触区（60）。

公开(公告)号：US09799757B2

公开(公告)日：2017-10-24

申请号：US12922665

申请日：2009-03-09

申请人： Evelyne Gridelet ,  Almudena Huerta ,  Pierre Goarin ,  Jan Sonsky

发明人： Evelyne Gridelet ,  Almudena Huerta ,  Pierre Goarin ,  Jan Sonsky

IPC分类号： G01N27/00 ,  H01L29/739 ,  G01N27/414

CPC分类号： H01L29/7391 ,  G01N27/4145

摘要： A sensor device (100, 2800) for detecting particles, the sensor device (100, 2800) comprising a substrate (102), a first doped region (104) formed in the substrate (102) by a first dopant of a first type of conductivity, a second doped region (106, 150) formed in the substrate (102) by a second dopant of a second type of conductivity which differs from the first type of conductivity, a depletion region (108) at a junction between the first doped region (104) and the second doped region (106, 150), a sensor active region (110) adapted to influence a property of the depletion region (108) in the presence of the particles, and a detection unit (112) adapted to detect the particles based on an electric measurement performed upon application of a predetermined reference voltage between the first doped region (104) and the second doped region (106, 150), the electric measurement being indicative of the presence of the particles in the sensor active region (110).

公开(公告)号：US20100314684A1

公开(公告)日：2010-12-16

申请号：US12866852

申请日：2009-02-09

申请人： Jan Sonsky ,  Radu Surdeanu

发明人： Jan Sonsky ,  Radu Surdeanu

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

摘要： The present invention relates to a FinFET with separate gates and to a method for fabricating the same. A dielectric gate-separation layer between first and second gate electrodes has an extension in a direction pointing from a first to a second gate layer that is smaller than a lateral extension of the fin between its opposite lateral faces. This structure corresponds with a processing method that starts from a covered basic FinFET structure with a continuous first gate layer, and proceeds to remove parts of the first gate layer and of a first gate-isolation layer through a contact opening to the gate layer. Subsequently, a replacement gate-isolation layer that at the same time forms the gate separation layer fabricated, followed by filling the tunnel with a replacement gate layer and a metal filling.

摘要翻译： 本发明涉及具有分离栅极的FinFET及其制造方法。 在第一和第二栅电极之间的电介质栅极分隔层在从第一栅极层到第二栅极层的方向上具有小于翅片在其相对侧面之间的横向延伸的方向上的延伸。 该结构对应于从具有连续的第一栅极层的覆盖的基本FinFET结构开始的处理方法，并且通过到栅极层的接触开口去除第一栅极层和第一栅极隔离层的部分。 随后，替代栅极隔离层同时形成栅极分离层，随后用替换栅极层和金属填充物填充隧道。

公开(公告)号：US07825011B2

公开(公告)日：2010-11-02

申请号：US11913255

申请日：2006-04-28

申请人： Philippe Meunier-Beillard ,  Jan Sonsky

发明人： Philippe Meunier-Beillard ,  Jan Sonsky

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L29/1054 ,  H01L21/76264 ,  H01L29/66575 ,  H01L29/78

摘要： The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (11) and a semiconductor body (12) in which at least one semiconductor element (1) is formed, wherein on the substrate (11) a semiconductor layer (2) is formed comprising a mixed crystal of silicon and germanium, further called the silicon-germanium layer (2) and having a lower surface close to the substrate (11) and an upper surface more remote from the substrate (11), and wherein the silicon-germanium layer (2) is subjected to an oxidizing treatment at a surface of the silicon-germanium layer (2) while the other surface of the silicon-germanium layer (2) is protected against the oxidizing treatment by a blocking layer (3). According to the invention, the blocking layer (3) is formed on the upper surface of the silicon-germanium layer (2), a cavity (5) is formed in the semiconductor body below the silicon-germanium layer (2) and the lower surface of the silicon-germanium layer (2) is subjected to the oxidizing treatment through the cavity (2). In this way, a device 10 may be obtained in which the surface of the silicon-germanium layer (2) after the oxidizing treatment does not suffer from roughening and/or germanium pile up. This enables e.g. to manufacture in particular a MOSFET on top of or in the silicon-germanium layer (2) with excellent properties and high yield.

摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，该半导体器件（10）包括其中形成有至少一个半导体元件（1）的衬底（11）和半导体本体（12），其中在衬底（11）上形成半导体层 （2）形成，包括硅和锗的混合晶体，进一步称为硅 - 锗层（2），并且具有靠近基板（11）的下表面和更远离基板（11）的上表面，以及 其中所述硅 - 锗层（2）在所述硅 - 锗层（2）的表面进行氧化处理，同时所述硅 - 锗层（2）的另一个表面被阻挡层 （3）。 根据本发明，在硅 - 锗层（2）的上表面上形成阻挡层（3），在硅 - 锗层（2）下面的半导体本体中形成空腔（5），下层 硅 - 锗层（2）的表面通过空腔（2）进行氧化处理。 以这种方式，可以获得其中氧化处理后的硅 - 锗层（2）的表面不会遭受粗糙化和/或锗堆积的器件10。 这使得例如。 特别是在硅 - 锗层（2）之上或之上制造具有优异性能和高产率的MOSFET。

公开(公告)号：US20100044760A1

公开(公告)日：2010-02-25

申请号：US12514940

申请日：2007-11-13

申请人： Gilberto Curatola ,  Mark Van Dal ,  Jan Sonsky

发明人： Gilberto Curatola ,  Mark Van Dal ,  Jan Sonsky

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region.

摘要翻译： 冲击电离MOSFET形成为从栅极偏移到垂直设置在器件结构内而不是水平的源/漏区之一。 半导体器件包括具有第一掺杂水平的第一源极/漏极区域; 具有第二掺杂水平并且与第一源极/漏极区相反的掺杂剂类型的第二源极/漏极区域，第一和第二源极/漏极区域由具有小于第一和/或第二源极/ 第二掺杂水平; 与所述中间区域电绝缘并设置在所述中间区域上的栅电极，所述第一和第二源极/漏极区域与所述栅电极横向对准; 其中形成与中间区域的边界的第一源极/漏极区域的整个部分与中间区域的顶部垂直地分离。