公开(公告)号：US07956399B2

公开(公告)日：2011-06-07

申请号：US11993296

申请日：2006-06-22

申请人： Wibo Daniel Van Noort ,  Jan Sonsky ,  Philippe Meunier-Beillard ,  Erwin Hijzen

发明人： Wibo Daniel Van Noort ,  Jan Sonsky ,  Philippe Meunier-Beillard ,  Erwin Hijzen

IPC分类号： H01L23/485

CPC分类号： H01L29/7378 ,  B82Y20/00 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/1087 ,  H01L29/41708 ,  H01L29/42384 ,  H01L29/66242 ,  H01L29/78 ,  H01L29/78645 ,  H01L29/78696 ,  H01L31/035236 ,  H01L31/1812 ,  Y02E10/50

摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention. Such a buried low resistance offers substantial advantages both for a bipolar transistor and for a MOS transistor.

摘要翻译： 本发明涉及具有衬底（11）和硅的半导体本体（12）的半导体器件（10），其包括具有晶体管（T）的有源区（A）和围绕有源区的无源区（P） （A），并且设置有金属材料的埋入导电区域（1），所述埋入导电区域连接到从所述半导体主体（12）的表面凹陷的金属材料的导电区域（2），所述埋入导电区域 区域（1）在半导体本体（12）的表面处可电连接。 根据本发明，在半导体本体（12）的有源区（A）的位置处形成掩埋导电区（1）。 以这种方式，可以使用与周围的硅具有完全不同的晶体学特性的金属材料，在半导体本体（12）的有源区（A）中局部地产生非常低的掩埋电阻。 这可以通过使用根据本发明的方法来实现。 这种埋下的低电阻为双极晶体管和MOS晶体管提供了显着的优点。

公开(公告)号：US20100047987A1

公开(公告)日：2010-02-25

申请号：US11913048

申请日：2006-04-24

申请人： Johannes Josephus Theodorus Marin Donkers ,  Erwin Hijzen ,  Wibo Daniel Van Noort

发明人： Johannes Josephus Theodorus Marin Donkers ,  Erwin Hijzen ,  Wibo Daniel Van Noort

IPC分类号： H01L21/331

CPC分类号： H01L29/66272 ,  H01L21/76224 ,  H01L27/0641 ,  H01L27/0647 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/732 ,  H01L29/735

摘要： The invention provides a method for fabricating a bipolar transistor applying a standard shallow trench isolation fabrication method to simultaneously form a vertical bipolar transistor (29) or a lateral bipolar transistor (49) in a first trench (5, 50) and a shallow trench isolation region (27, 270) in a second trench (7, 70). Further, the fabrication method may simultaneously form a vertical bipolar transistor (27) in the first trench (5, 50), a lateral bipolar transistor (49) in a third trench and a shallow trench isolation region (27, 270) in the second trench (7, 70).

摘要翻译： 本发明提供一种用于制造双极晶体管的方法，其应用标准浅沟槽隔离制造方法，以在第一沟槽（5,50）和浅沟槽隔离中同时形成垂直双极晶体管（29）或横向双极晶体管（49） 区域（27,270）在第二沟槽（7,70）中。 此外，制造方法可以同时在第一沟槽（5,50）中形成垂直双极晶体管（27），在第三沟槽中形成横向双极晶体管（49），在第二沟槽中形成浅沟槽隔离区域（27,270） 沟槽（7,70）。

公开(公告)号：US08729652B2

公开(公告)日：2014-05-20

申请号：US12282932

申请日：2007-03-13

申请人： Anco Heringa ,  Erik Jan Lous ,  Wibo Daniel Van Noort ,  Wilhelmus Cornelis Maria Peters ,  Joost Willem Christiaan Veltkamp

发明人： Anco Heringa ,  Erik Jan Lous ,  Wibo Daniel Van Noort ,  Wilhelmus Cornelis Maria Peters ,  Joost Willem Christiaan Veltkamp

IPC分类号： H01L31/115

CPC分类号： G01T1/2018 ,  H01L27/14659 ,  H01L27/14663 ,  H01L31/115

摘要： The invention provides a semiconductor device (11) for radiation detection, which comprises a substrate region (1) of a substrate semiconductor material, such as silicon, and a detection region (3) at a surface of the semiconductor device (11), in which detection region (3) charge carriers of a first conductivity type, such as electrons, are generated and detected upon incidence of electromagnetic radiation (L) on the semiconductor device (11). The semiconductor device (11) further comprises a barrier region (2,5,14) of a barrier semiconductor material or an isolation material, which barrier region (2,5,14) is an obstacle between the substrate region (1) and the detection region (3) for charge carriers that are generated in the substrate region (1) by penetration of ionizing radiation (X), such as X-rays, into the substrate region (1). This way the invention provides a semiconductor device (11) for radiation detection in which the influence on the performance of the semiconductor device (11) of ionizing radiation (X), such as X-rays, that penetrates into the substrate region (1) is reduced.

摘要翻译： 本发明提供了一种用于放射线检测的半导体器件（11），其包括诸如硅的衬底半导体材料的衬底区域（1）和在半导体器件（11）的表面处的检测区域（3） 在半导体器件（11）上的电磁辐射（L）入射时，产生并检测出检测区域（3）对第一导电类型（例如电子）的载流子。 半导体器件（11）还包括阻挡半导体材料或隔离材料的阻挡区域（2,5,14），所述阻挡区域（2,5,14）是衬底区域（1）和衬底区域 用于通过诸如X射线的电离辐射（X）穿透而在衬底区域（1）中产生的电荷载体的检测区域（3）。 这样，本发明提供了一种用于放射线检测的半导体器件（11），其中对穿透到衬底区域（1）中的诸如X射线的电离辐射（X）的半导体器件（11）的性能的影响， 降低了。

公开(公告)号：US07659600B2

公开(公告)日：2010-02-09

申请号：US11568196

申请日：2005-04-12

申请人： Wibo Daniel Van Noort

发明人： Wibo Daniel Van Noort

IPC分类号： H01L29/00

CPC分类号： H01L29/0638 ,  H01L21/761 ,  H01L27/08

摘要： The invention relates to a semiconductor device (10) with a semiconductor body (1) comprising a high-ohmic semiconductor substrate (2) which is covered with a dielectric layer (3) containing charges, on which dielectric layer one or more passive electronic components (4) comprising conductor tracks (4) are present, and at the location of the passive elements (4) a semiconductor region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), a first conductivity-type conducting channel induced in the semiconductor substrate (2) by the charges being interrupted by, and at the location of, the semiconductor region (5).According to the invention, the semiconductor region (5) is monocrystalline and of a second conductivity type, opposite to the first conductivity type. In this way the charge of an induced channel is locally compensated by the charge of the semiconductor regions (5). The device (10) has a very low high-frequency power loss, because the inversion channel is interrupted at the location of the semiconductor region (5). The device (10) further allows for a higher thermal budget and thus for the integration of active semiconductor elements (8) into the semiconductor body (1). Preferably, the semiconductor region (5) comprises a large number of strip-shaped sub-regions (5A, 5B, 5C).

摘要翻译： 本发明涉及一种具有半导体本体（1）的半导体器件（10），该半导体器件（1）包括用包含电荷的介电层（3）覆盖的高欧姆半导体衬底（2），电介质层上有一个或多个无源电子部件 （4），并且在无源元件（4）的位置处，在半导体衬底（2）和电介质层（3,4）之间的界面处存在半导体区域（5） 由在半导体区域（5）中间和位置处的电荷在半导体衬底（2）中感应的第一导电型导电沟道。 根据本发明，半导体区域（5）是与第一导电类型相反的单晶并且具有第二导电类型。 以这种方式，通过半导体区域（5）的电荷对感应通道的电荷进行局部补偿。 由于反转通道在半导体区域（5）的位置被中断，所以器件（10）具有非常低的高频功率损耗。 器件（10）进一步允许较高的热预算，从而将有源半导体元件（8）集成到半导体本体（1）中。 优选地，半导体区域（5）包括大量条形子区域（5A，5B，5C）。

公开(公告)号：US20080169527A1

公开(公告)日：2008-07-17

申请号：US11568196

申请日：2005-04-12

申请人： Wibo Daniel Van Noort

发明人： Wibo Daniel Van Noort

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L29/0638 ,  H01L21/761 ,  H01L27/08

摘要： The invention relates to a semiconductor device (10) with a semiconductor body (1) comprising a high-ohmic semiconductor substrate (2) which is covered with a dielectric layer (3) containing charges, on which dielectric layer one or more passive electronic components (4) comprising conductor tracks (4) are present, and at the location of the passive elements (4) a semiconductor region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), a first conductivity-type conducting channel induced in the semiconductor substrate (2) by the charges being interrupted by, and at the location of, the semiconductor region (5).According to the invention, the semiconductor region (5) is monocrystalline and of a second conductivity type, opposite to the first conductivity type. In this way the charge of an induced channel is locally compensated by the charge of the semiconductor regions (5). The device (10) has a very low high-frequency power loss, because the inversion channel is interrupted at the location of the semiconductor region (5). The device (10) further allows for a higher thermal budget and thus for the integration of active semiconductor elements (8) into the semiconductor body (1). Preferably, the semiconductor region (5) comprises a large number of strip-shaped sub-regions (5A, 5B, 5C).

摘要翻译： 本发明涉及一种具有半导体本体（1）的半导体器件（10），该半导体器件（1）包括用包含电荷的介电层（3）覆盖的高欧姆半导体衬底（2），电介质层上有一个或多个无源电子部件 （4），并且在无源元件（4）的位置处，在半导体衬底（2）和电介质层（3,4）之间的界面处存在半导体区域（5） 由在半导体区域（5）中间和位置处的电荷在半导体衬底（2）中感应的第一导电型导电沟道。 根据本发明，半导体区域（5）是与第一导电类型相反的单晶并且具有第二导电类型。 以这种方式，通过半导体区域（5）的电荷对感应通道的电荷进行局部补偿。 由于反转通道在半导体区域（5）的位置被中断，所以器件（10）具有非常低的高频功率损耗。 器件（10）进一步允许较高的热预算，从而将有源半导体元件（8）集成到半导体本体（1）中。 优选地，半导体区域（5）包括大量条形子区域（5A，5B，5C）。

公开(公告)号：US07381656B2

公开(公告)日：2008-06-03

申请号：US10599032

申请日：2005-03-11

申请人： Wibo Daniel Van Noort ,  Eyup Aksen

发明人： Wibo Daniel Van Noort ,  Eyup Aksen

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76229 ,  H01L21/02002

摘要： The invention relates to a method of manufacturing a semiconductor device comprising a substrate (1) and a semiconductor body (2) in which at least one semiconductor element is formed, wherein, in the semiconductor body (2), a semiconductor island (3) is formed by forming a first cavity (4) in the surface of the semiconductor body (2), the walls of said first cavity being covered with a first dielectric layer (6), after which, by means of underetching through the bottom of the cavity (4), a lateral part of the semiconductor body (2) is removed, thereby forming a cavity (20) in the semiconductor body (2) above which the semiconductor island (3) is formed, and wherein a second cavity (5) is formed in the surface of the semiconductor body (2), the walls of said second cavity being covered with a second dielectric layer, and one of the walls covered with said second dielectric layer forming a side wall of the semiconductor island (3).According to the invention, the same dielectric layer (6) is chosen for the first and the second dielectric layer, a lateral size of the second cavity (5) and the thickness of the dielectric layer (6) are chosen such that the second cavity (5) becomes nearly completely filled by the dielectric layer (6), and the lateral sizes of the first cavity (4) are chosen such that the walls and the bottom of the first cavity (4) are provided with a uniform coating by the dielectric layer (6). In this way, a semiconductor island (3) which is isolated from its environment can be made using a minimum number of (masking) steps.

摘要翻译： 本发明涉及一种制造半导体器件的方法，该半导体器件包括其中形成有至少一个半导体元件的衬底（1）和半导体本体（2），其中在半导体本体（2）中，半导体岛（3） 通过在半导体本体（2）的表面中形成第一空腔（4）形成，所述第一腔的壁被第一介电层（6）覆盖，之后借助于穿过半导体本体 空腔（4），半导体主体（2）的侧面部分被去除，从而在半导体主体（2）中形成空腔（20），在半导体主体（2）之上形成半导体岛（3），并且其中第二腔 ）形成在半导体本体（2）的表面中，所述第二腔的壁被第二电介质层覆盖，并且覆盖有形成半导体岛（3）的侧壁的所述第二电介质层的一个壁， 。 根据本发明，为第一和第二介电层选择相同的介电层（6），第二腔（5）的横向尺寸和电介质层（6）的厚度被选择为使得第二腔 （5）变得几乎完全被电介质层（6）填充，并且第一空腔（4）的横向尺寸被选择为使得第一空腔（4）的壁和底部被均匀地涂覆 电介质层（6）。 以这种方式，可以使用最少数量（掩蔽）步骤来制造与其环境隔离的半导体岛（3）。

公开(公告)号：US20080318375A1

公开(公告)日：2008-12-25

申请号：US11815100

申请日：2006-01-23

申请人： Wibo Daniel Van Noort ,  Franciscus Petrus Widdershoven ,  Radu Surdeanu

发明人： Wibo Daniel Van Noort ,  Franciscus Petrus Widdershoven ,  Radu Surdeanu

IPC分类号： H01L21/8238

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7854

摘要： The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first layer (3) and a second layer (4) are formed, after which the top surface of the protrusion (2) is exposed. A portion of the first layer (3) is selectively removed relative to the protrusion (2) and the second layer (4), thereby creating a fin (6) and a trench (5). Also a method is presented to form a plurality of fins (6) and trenches (5). The dual-gate FET is created by forming a gate electrode (7) in the trench(es) (5) and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.

摘要翻译： 本发明提供了一种使用常规半导体处理技术制造极短的双栅极FET的方法，其具有非常小且可重现的鳍，其间距和宽度都小于可以用光刻技术获得的。 在基板（1）上的突起（2）上形成第一层（3）和第二层（4），然后露出突起（2）的上表面。 相对于突起（2）和第二层（4），第一层（3）的一部分被选择性地去除，从而形成翅片（6）和沟槽（5）。 还提出了形成多个翅片（6）和沟槽（5）的方法。 通过在沟槽（5）中形成栅电极（7）和源极和漏极区域来产生双栅极FET。 此外，提出了一种制造具有可分别偏置的两个栅电极的极短的非对称双栅极FET的方法。

公开(公告)号：US07098530B2

公开(公告)日：2006-08-29

申请号：US10560004

申请日：2004-06-08

申请人： Andreas Bernardus Maria Jansman ,  Ronald Dekker ,  Godefridus Andrianus Maria Hurkx ,  Wibo Daniel Van Noort ,  Antonius Lucien Adrianus Maria Kemmeren

发明人： Andreas Bernardus Maria Jansman ,  Ronald Dekker ,  Godefridus Andrianus Maria Hurkx ,  Wibo Daniel Van Noort ,  Antonius Lucien Adrianus Maria Kemmeren

IPC分类号： H01L23/58

CPC分类号： H01L24/82 ,  H01L23/36 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/24 ,  H01L2223/6644 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15192 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

摘要： The electronic device comprises a substrate (1) with a cavity (6) in which an active device (8) is present. On the first side (2) of the substrate an interconnect structure (17) extends over the cavity and the substrate. On the second side (3) of the substrate to which the cavity extends, a heat sink (23) is available. The device is particularly suitable for use at high frequencies, for instance higher than 2 GHz and under conditions of high dissipation.

摘要翻译： 电子设备包括具有空腔（6）的衬底（1），其中存在有源器件（8）。 在衬底的第一侧（2）上，互连结构（17）在空腔和衬底上延伸。 在空腔延伸的基板的第二面（3）上，散热片（23）是可用的。 该装置特别适用于高频率，例如高于2GHz，在高耗散条件下使用。

公开(公告)号：US08294203B2

公开(公告)日：2012-10-23

申请号：US11574337

申请日：2005-09-02

申请人： Wibo Daniel Van Noort ,  Peter Deixler

发明人： Wibo Daniel Van Noort ,  Peter Deixler

IPC分类号： H01L29/76

CPC分类号： H01L21/743 ,  H01L21/763

摘要： Electrically isolated, deep trench isolation (DTI) structures, are formed in a wafer, and a portion of the DTI structures are converted to electrically connected structures to provide a shielding function, or to provide connection to deep buried layers. In one aspect, DTI structures include a polysilicon filling over a liner layer disposed on the inner surface of a deep trench, the polysilicon is removed by isotropic etching, and the deep trench is re-filled with a conductive material. Alternatively, the polysilicon filling remains and a contact is formed to provide an electrical connection to the polysilicon. In another aspect, a deep trench is disposed in the wafer such that a lower portion thereof is located within a deep buried layer, and after the polysilicon is removed, an anisotropic etch removes a portion of the deep trench liner from the bottom of the deep trench, thereby allowing a tungsten deposition to make electrical contact with the deep buried layer.

摘要翻译： 在晶片中形成电隔离的深沟槽隔离（DTI）结构，并且将DTI结构的一部分转换成电连接的结构以提供屏蔽功能，或提供与深埋层的连接。 一方面，DTI结构包括在深沟槽的内表面上的衬垫层上的多晶硅填充，通过各向同性蚀刻去除多晶硅，并且用导电材料重新填充深沟槽。 或者，残留多晶硅填充物并形成接触以提供与多晶硅的电连接。 在另一方面，深沟槽设置在晶片中，使得其下部位于深埋层内，并且在多晶硅被去除之后，各向异性蚀刻从深层底部去除一部分深沟槽衬垫 沟槽，从而允许钨沉积与深埋层电接触。

公开(公告)号：US20110147884A1

公开(公告)日：2011-06-23

申请号：US11574337

申请日：2005-09-02

申请人： Wibo Daniel Van Noort ,  Peter Deixler

发明人： Wibo Daniel Van Noort ,  Peter Deixler

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/743 ,  H01L21/763

摘要： Electrically isolated, deep trench isolation (DTI) structures, are formed in a wafer, and a portion of the DTI structures are converted to electrically connected structures to provide a shielding function, or to provide connection to deep buried layers. In one aspect, DTI structures include a polysilicon filling over a liner layer disposed on the inner surface of a deep trench, the polysilicon is removed by isotropic etching, and the deep trench is re-filled with a conductive material. Alternatively, the polysilicon filling remains and a contact is formed to provide an electrical connection to the polysilicon. In another aspect, a deep trench is disposed in the wafer such that a lower portion thereof is located within a deep buried layer, and after the polysilicon is removed, an anisotropic etch removes a portion of the deep trench liner from the bottom of the deep trench, thereby allowing a tungsten deposition to make electrical contact with the deep buried layer.

摘要翻译： 在晶片中形成电隔离的深沟槽隔离（DTI）结构，并且将一部分DTI结构转换成电连接的结构以提供屏蔽功能，或提供与深埋层的连接。 一方面，DTI结构包括在深沟槽的内表面上的衬垫层上的多晶硅填充，通过各向同性蚀刻去除多晶硅，并且用导电材料重新填充深沟槽。 或者，残留多晶硅填充物并形成接触以提供与多晶硅的电连接。 在另一方面，深沟槽设置在晶片中，使得其下部位于深埋层内，并且在去除多晶硅之后，各向异性蚀刻从深层底部去除一部分深沟槽衬垫 沟槽，从而允许钨沉积与深埋层电接触。