公开(公告)号：US20070224845A1

公开(公告)日：2007-09-27

申请号：US11386343

申请日：2006-03-22

申请人： Wiren Becker ,  William Brodsky ,  Evan Colgan ,  Michael McAllister ,  Edward Seminaro ,  John Torok

发明人： Wiren Becker ,  William Brodsky ,  Evan Colgan ,  Michael McAllister ,  Edward Seminaro ,  John Torok

IPC分类号： H01R12/00

CPC分类号： H01L23/49838 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/09701 ,  H05K1/141 ,  H05K3/325 ,  H05K3/368

摘要： Apparatus and methods are provided for constructing electronic package structures using LGA (land grid array) module-to-board connectors that are designed to provide higher count I/O interconnections by expanding LGA area, but without having to increase chip module footprint or reduce the pitch of area array I/O contacts of an LGA interposer or circuit board beyond practical limits.

摘要翻译： 提供的装置和方法用于构建使用LGA（地面栅格阵列）模块到板连接器的电子封装结构，其被设计为通过扩展LGA面积来提供更高计数的I / O互连，但不必增加芯片模块占用面积或减少 LGA插入器或电路板的面积阵列I / O触点的间距超出实际限制。

公开(公告)号：US20060182214A1

公开(公告)日：2006-08-17

申请号：US11056767

申请日：2005-02-11

申请人： Charlie Hwang ,  Timothy McNamara ,  Ching-Lung Tong ,  Wiren Becker

发明人： Charlie Hwang ,  Timothy McNamara ,  Ching-Lung Tong ,  Wiren Becker

IPC分类号： H04L7/02

CPC分类号： H03L7/06 ,  G06F1/10

摘要： A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the “time zero” of the chips.

摘要翻译： 一种在多芯片系统中自同步时钟的方法，通过分配一个芯片作为主芯片，将其它芯片分配为从芯片。 训练信号从主芯片发送到从芯片，以确定从主芯片到从芯片的延迟，然后发送同步信号以同步芯片的“时间零”。

公开(公告)号：US20060087813A1

公开(公告)日：2006-04-27

申请号：US10972868

申请日：2004-10-25

申请人： Wiren Becker ,  Joseph Corrado ,  Ethan Cruz ,  Michael Fisher ,  Gary Goth

发明人： Wiren Becker ,  Joseph Corrado ,  Ethan Cruz ,  Michael Fisher ,  Gary Goth

IPC分类号： H05K1/00

CPC分类号： H05K7/20563 ,  G06F1/183 ,  G06F1/20

摘要： A system for airflow management in an electronic enclosure includes a backplane assembly having at least one backplane connector, at least one daughter card, and components disposed on the daughter card oriented to facilitate front-to-back airflow, wherein inlet cooling air impinges on the backplane assembly and splits into at least two flow portions flowing in different directions along a surface defining the backplane assembly

摘要翻译： 一种用于电子外壳中的气流管理的系统包括背板组件，该背板组件具有至少一个背板连接器，至少一个子卡，以及设置在子卡上的部件，其定向成便于前后气流，其中入口冷却空气冲击 底板组件，并分成沿着限定背板组件的表面沿不同方向流动的至少两个流动部分

公开(公告)号：US20070109726A1

公开(公告)日：2007-05-17

申请号：US11281688

申请日：2005-11-17

申请人： Wiren Becker ,  Bruce Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

发明人： Wiren Becker ,  Bruce Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

IPC分类号： H02B1/00

CPC分类号： H05K1/0262 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663

摘要： The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.

摘要翻译： 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各个平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

公开(公告)号：US20060182212A1

公开(公告)日：2006-08-17

申请号：US11363871

申请日：2006-02-28

申请人： Charlie Hwang ,  Wiren Becker ,  Timothy McNamara ,  Ching-Lung Tong

发明人： Charlie Hwang ,  Wiren Becker ,  Timothy McNamara ,  Ching-Lung Tong

IPC分类号： H04L7/00

CPC分类号： G06F1/10 ,  H03L7/06

摘要： A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically. This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time

摘要翻译： 一种用于产生多芯片系统的同步信号的时钟发生器电路。 时钟发生器电路包括从参考时钟和具有边缘检测逻辑的芯片全局时钟产生同步信号。 在具有多个芯片的高性能服务器系统设计中，服务器系统的常见做法是使用反馈时钟和延迟参考时钟来生成同步信号。 所产生的同步信号被传送到由全局时钟计时的锁存器，以用于芯片同步功能。 随着系统时钟频率被推高，由反馈时钟所产生的所生成的同步信号与由全局时钟计时的接收锁存器之间的相位差成为这个信号不能被确定地传送的循环时间的大部分。 本发明解决了不确定性问题，并允许确定地产生同步信号，而不依赖于芯片全局时钟周期时间

公开(公告)号：US20070111576A1

公开(公告)日：2007-05-17

申请号：US11282041

申请日：2005-11-17

申请人： Wiren Becker ,  Bruce Chamberlin ,  Gerald Fahr ,  Roland Frech ,  Dierk Kaller ,  George Katopis ,  Erich Klink ,  Thomas-Michael Winkel

发明人： Wiren Becker ,  Bruce Chamberlin ,  Gerald Fahr ,  Roland Frech ,  Dierk Kaller ,  George Katopis ,  Erich Klink ,  Thomas-Michael Winkel

IPC分类号： H01R13/15

CPC分类号： H05K1/11 ,  H01R12/523 ,  H01R13/6466 ,  H01R13/6471 ,  H01R13/6589 ,  H01R13/6625 ,  H05K1/0216 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/10189

摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring. In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.

摘要翻译： 本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。 特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。 为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容 在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

公开(公告)号：US20070046335A1

公开(公告)日：2007-03-01

申请号：US11211955

申请日：2005-08-25

申请人： Wiren Becker ,  Anand Haridass ,  Bao Truong

发明人： Wiren Becker ,  Anand Haridass ,  Bao Truong

IPC分类号： H03K19/00

CPC分类号： H03K5/00 ,  H03K5/135 ,  H04L25/0276

摘要： Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an Nx1 MUX. The Nx1 MUX is controlled by the skew controller. The output of the Nx1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.

摘要翻译： 数据总线被配置为由数据信号驱动的N个差分信道及其通过两个片外驱动器（OCD）的补码。 每个OCD之前都有可编程延迟元件和双向MUX。 两个数据通道传输数据信号或由偏斜控制器的选择信号确定的公共时钟信号。 差分信号在差分接收机和相位检测器中被接收。 每个差分信道中的相位检测器的输出通过Nx1 MUX进行路由。 Nx1 MUX由偏斜控制器控制。 Nx1 MUX的输出作为相位误差反馈信号反馈到歪斜控制器。 顺序地选择每个差分数据通道，并且调整可编程延迟，直到来自所选相位检测器的相位误差反馈信号达到预定的最小允许值。 可以进行定期调整以进行校准。

公开(公告)号：US06437252B1

公开(公告)日：2002-08-20

申请号：US09741455

申请日：2000-12-19

申请人： Simone Rehm ,  Roland Frech ,  Erich Klink ,  Helmut Virag ,  Thomas-Michael Winkel ,  Wiren Becker ,  Bruce Chamberlin ,  Wai Ma

发明人： Simone Rehm ,  Roland Frech ,  Erich Klink ,  Helmut Virag ,  Thomas-Michael Winkel ,  Wiren Becker ,  Bruce Chamberlin ,  Wai Ma

IPC分类号： H05K102

摘要： Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.