公开(公告)号：US20160155688A9

公开(公告)日：2016-06-02

申请号：US14033140

申请日：2013-09-20

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495

CPC分类号： H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/16245 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

公开(公告)号：US09391005B2

公开(公告)日：2016-07-12

申请号：US14033140

申请日：2013-09-20

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495

CPC分类号： H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/16245 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

摘要翻译： 功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。 桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

公开(公告)号：US20120235289A1

公开(公告)日：2012-09-20

申请号：US13480391

申请日：2012-05-24

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L24/73 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1184 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16245 ,  H01L2224/2784 ,  H01L2224/291 ,  H01L2224/3015 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16151 ,  H01L2924/167 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/92 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/48247 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/73103 ,  H01L2924/00

摘要： A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

摘要翻译： 功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。 桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

公开(公告)号：US08564110B2

公开(公告)日：2013-10-22

申请号：US13480391

申请日：2012-05-24

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495

CPC分类号： H01L24/73 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1184 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16245 ,  H01L2224/2784 ,  H01L2224/291 ,  H01L2224/3015 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16151 ,  H01L2924/167 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/92 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/48247 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/73103 ,  H01L2924/00

摘要： A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

摘要翻译： 功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。 桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

公开(公告)号：US20150087114A1

公开(公告)日：2015-03-26

申请号：US14033140

申请日：2013-09-20

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495

CPC分类号： H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/16245 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

摘要翻译： 功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。 桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

公开(公告)号：US20140242756A1

公开(公告)日：2014-08-28

申请号：US13775212

申请日：2013-02-24

申请人： Yan Xun Xue ,  Ping Huang ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Lei Shi ,  Liang Zhao ,  Ping Li Wu ,  Lei Duan ,  Yuping Gong

发明人： Yan Xun Xue ,  Ping Huang ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Lei Shi ,  Liang Zhao ,  Ping Li Wu ,  Lei Duan ,  Yuping Gong

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L2224/1184 ,  H01L2224/13101 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.

摘要翻译： 一种用于在倒装芯片工艺中制备半导体器件的方法包括形成围绕每个半导体芯片的深槽; 沉积第一塑料封装材料以形成覆盖半导体晶片的前表面并填充深槽的第一塑料封装层; 在研磨后在半导体晶片的背面沉积金属层; 研磨金属层的最外部分，从而形成位于未被金属层覆盖的半导体晶片的边缘周围的背面的环形区域; 沿着由填充有第一塑料包装材料的每个深槽的两端形成的直线切割填充在深槽中的第一塑料封装层，半导体晶片，金属层和第一塑料封装材料; 并且拾取半导体器件并安装在衬底上，而不会翻转半导体器件。

公开(公告)号：US08865523B2

公开(公告)日：2014-10-21

申请号：US13833341

申请日：2013-03-15

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495 ,  H01L21/78

CPC分类号： H01L23/49562 ,  H01L21/561 ,  H01L21/78 ,  H01L23/06 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49568 ,  H01L2224/32245 ,  H01L2924/13091 ,  H01L2924/00

摘要： A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

摘要翻译： 一种制造半导体封装器件的方法包括将引线框架安装在模制半导体芯片的底部，该底部具有覆盖半导体芯片的顶面的第一塑料封装体，用第二塑料封装体封装引线框和半导体芯片 导电接触体的顶表面电连接到半导体芯片的顶表面上的电极，并暴露在组件结构的顶表面上的导电焊盘，以通过导电接触体提供与电极的外部电连接。

公开(公告)号：US20140264805A1

公开(公告)日：2014-09-18

申请号：US13833341

申请日：2013-03-15

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495 ,  H01L21/78

CPC分类号： H01L23/49562 ,  H01L21/561 ,  H01L21/78 ,  H01L23/06 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49568 ,  H01L2224/32245 ,  H01L2924/13091 ,  H01L2924/00

摘要： A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

摘要翻译： 一种制造半导体封装器件的方法包括将引线框架安装在模制半导体芯片的底部，该底部具有覆盖半导体芯片的顶面的第一塑料封装体，用第二塑料封装体封装引线框和半导体芯片 导电接触体的顶表面电连接到半导体芯片的顶表面上的电极，并暴露在组件结构的顶表面上的导电焊盘，以通过导电接触体提供与电极的外部电连接。

公开(公告)号：US08952509B1

公开(公告)日：2015-02-10

申请号：US14031283

申请日：2013-09-19

申请人： Hamza Yilmaz ,  Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Xiaotian Zhang ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Liang Zhao ,  YuPing Gong ,  GuoFeng Lian

发明人： Hamza Yilmaz ,  Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Xiaotian Zhang ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Liang Zhao ,  YuPing Gong ,  GuoFeng Lian

IPC分类号： H01L25/07 ,  H01L23/495 ,  H01L25/00

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.

摘要翻译： 本发明公开了一种叠层双MOSFET封装结构及其制备方法。 堆叠双MOSFET封装结构包括具有管芯焊盘，第一引线和第二引线的引线框架单元; 第一芯片翻转并附接在模板的主桨的顶表面上; 附接在主桨的底表面上的第二芯片; 以及安装在翻转的第一芯片的背面上并将第一芯片背面的电极电连接到第一引线的金属夹。 布置在第二芯片的前面的每个电极上的金属凸块的顶表面，模板的模具销的底表面，第二引线的引脚的底表面和第一引脚的底表面 导线位于同一平面上。

公开(公告)号：US08436429B2

公开(公告)日：2013-05-07

申请号：US13118445

申请日：2011-05-29

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

IPC分类号： H01L27/088

CPC分类号： H01L23/49562 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

摘要翻译： 叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。 在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。 安装夹在第一半导体芯片的背面连接到电极。 第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。