公开(公告)号：US08952509B1

公开(公告)日：2015-02-10

申请号：US14031283

申请日：2013-09-19

申请人： Hamza Yilmaz ,  Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Xiaotian Zhang ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Liang Zhao ,  YuPing Gong ,  GuoFeng Lian

发明人： Hamza Yilmaz ,  Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Xiaotian Zhang ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Liang Zhao ,  YuPing Gong ,  GuoFeng Lian

IPC分类号： H01L25/07 ,  H01L23/495 ,  H01L25/00

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.

摘要翻译： 本发明公开了一种叠层双MOSFET封装结构及其制备方法。 堆叠双MOSFET封装结构包括具有管芯焊盘，第一引线和第二引线的引线框架单元; 第一芯片翻转并附接在模板的主桨的顶表面上; 附接在主桨的底表面上的第二芯片; 以及安装在翻转的第一芯片的背面上并将第一芯片背面的电极电连接到第一引线的金属夹。 布置在第二芯片的前面的每个电极上的金属凸块的顶表面，模板的模具销的底表面，第二引线的引脚的底表面和第一引脚的底表面 导线位于同一平面上。

公开(公告)号：US08841167B1

公开(公告)日：2014-09-23

申请号：US13951772

申请日：2013-07-26

申请人： Yuping Gong ,  Yan Xun Xue ,  Liang Zhao

发明人： Yuping Gong ,  Yan Xun Xue ,  Liang Zhao

IPC分类号： H01L21/50 ,  H01L21/56 ,  H01L23/495 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L24/34 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40475 ,  H01L2224/4103 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

摘要翻译： 公开了一种用于共包装高侧（HS）和低侧（LS）半导体芯片）的半导体封装方法。 HS和LS半导体芯片附接到引线框架的两个相对侧，LS芯片的底部漏电极连接到引线框架的顶侧，HS芯片的顶部源极连接到 引线框架通过焊球。 HS芯片，引线框架和LS芯片的堆叠配置减少了封装尺寸。 覆盖暴露在封装主体外部的HS芯片的底部的底部金属层提供电连接和热传导。

公开(公告)号：US08778735B1

公开(公告)日：2014-07-15

申请号：US13931854

申请日：2013-06-29

申请人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

IPC分类号： H01L21/00 ,  H01L21/304 ,  H01L21/78

CPC分类号： H01L21/304 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/27 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

摘要： A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

摘要翻译： WLCSP方法包括：在芯片的焊盘上沉积金属凸块; 在晶片的前表面形成第一包装层以覆盖金属凸块，同时在晶片边缘形成未覆盖的环，以露出位于两个相邻芯片之间的每个划线的端部; 稀释第一包装层以暴露金属凸块; 通过沿着未被覆盖的环的前表面上暴露的划线的两端延伸的直线切割沿着每个划线在第一包装层的前表面上形成凹槽; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 在凹陷空间中在晶片的底面沉积金属层; 切断晶片的边缘部分; 以及通过沿着沟槽切割第一包装层，晶片和金属层，从晶片分离单个芯片。

公开(公告)号：US08563361B2

公开(公告)日：2013-10-22

申请号：US13547358

申请日：2012-07-12

申请人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  H01L23/3157 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/13091 ,  H01L2924/00

摘要： A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

摘要翻译： WLCSP方法包括：在芯片的焊盘上沉积金属凸块; 在晶片的前表面形成第一包装层以覆盖金属凸块，同时在晶片边缘形成未覆盖的环，以露出位于两个相邻芯片之间的每个划线的端部; 稀释第一包装层以暴露金属凸块; 通过沿着未被覆盖的环的前表面上暴露的划线的两端延伸的直线切割沿着每个划线在第一包装层的前表面上形成凹槽; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 在凹陷空间中在晶片的底面沉积金属层; 切断晶片的边缘部分; 以及通过沿着沟槽切割第一包装层，晶片和金属层，从晶片分离单个芯片。

公开(公告)号：US08519520B2

公开(公告)日：2013-08-27

申请号：US13302077

申请日：2011-11-22

申请人： YuPing Gong ,  Yan Xun Xue ,  Liang Zhao

发明人： YuPing Gong ,  Yan Xun Xue ,  Liang Zhao

IPC分类号： H01L23/495 ,  H01L23/34

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

摘要翻译： 公开了一种用于共包装高侧（HS）和低侧（LS）半导体芯片）的半导体封装方法。 HS和LS半导体芯片附接到引线框架的两个相对侧，LS芯片的底部漏电极连接到引线框架的顶侧，HS芯片的顶部源极连接到 引线框架通过焊球。 HS芯片，引线框架和LS芯片的堆叠配置减少了封装尺寸。 覆盖暴露在封装主体外部的HS芯片的底部的底部金属层提供电连接和热传导。

公开(公告)号：US20130075884A1

公开(公告)日：2013-03-28

申请号：US13302077

申请日：2011-11-22

申请人： YuPing Gong ,  Yan Xun Xue ,  Liang Zhao

发明人： YuPing Gong ,  Yan Xun Xue ,  Liang Zhao

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

摘要翻译： 公开了一种用于共包装高侧（HS）和低侧（LS）半导体芯片）的半导体封装方法。 HS和LS半导体芯片附接到引线框架的两个相对侧，LS芯片的底部漏电极连接到引线框架的顶侧，HS芯片的顶部源极连接到 引线框架通过焊球。 HS芯片，引线框架和LS芯片的堆叠配置减少了封装尺寸。 覆盖暴露在封装主体外部的HS芯片的底部的底部金属层提供电连接和热传导。

公开(公告)号：US08344499B2

公开(公告)日：2013-01-01

申请号：US13421864

申请日：2012-03-16

申请人： Yuping Gong ,  Yan Xun Xue

发明人： Yuping Gong ,  Yan Xun Xue

IPC分类号： H01L29/78

CPC分类号： H01L23/49562 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0346 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/83191 ,  H01L2224/8485 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/01028 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00012

摘要： A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.

摘要翻译： 一种制造芯片暴露半导体封装的方法，包括以下步骤：在晶片上的每个芯片的正面上电镀多个电极; 研磨晶片的背面并沉积后金属，然后分离每个芯片; 安装具有粘附在引线框架的多个桨叶的前面上的电镀电极的芯片; 将胶带粘附在背面金属上并用模塑料包封; 移除带子并穿过引线框架和模塑料形成多个封装的半导体器件。

公开(公告)号：US20120164793A1

公开(公告)日：2012-06-28

申请号：US13045407

申请日：2011-03-10

申请人： Lei Shi ,  Yan Xun Xue ,  Yuping Gong

发明人： Lei Shi ,  Yan Xun Xue ,  Yuping Gong

IPC分类号： H01L21/56

CPC分类号： H01L21/4832 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2224/83

摘要： Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

摘要翻译： 公开了专门用于倒装芯片垂直功率器件的封装半导体器件的制备方法。 在这些方法中，将垂直半导体芯片倒装芯片连接到引线框架，然后用塑料包装材料封装。 然后将封装的芯片变薄到预定厚度。 通过蚀刻至少连接的引线框架的底部部分，形成连接芯片与外部电路的接触端子。

公开(公告)号：US08987878B2

公开(公告)日：2015-03-24

申请号：US12916086

申请日：2010-10-29

申请人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

发明人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

IPC分类号： H01L23/495 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L29/06

CPC分类号： H01L21/6836 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76897 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L24/94 ,  H01L25/50 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/051 ,  H01L2224/05139 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/1184 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.

摘要翻译： 无基底复合功率半导体器件可以包括薄衬底和位于衬底顶表面上的顶金属层。 衬底和外延层的总厚度可以小于25微米。 焊料凸块形成在顶部金属层的顶部，并且模塑料围绕焊料凸起并且使焊料凸块至少部分暴露。

公开(公告)号：US20130210195A1

公开(公告)日：2013-08-15

申请号：US13547358

申请日：2012-07-12

申请人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

IPC分类号： H01L21/78

CPC分类号： H01L21/563 ,  H01L23/3157 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/13091 ,  H01L2924/00

摘要： A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

摘要翻译： WLCSP方法包括：在芯片的焊盘上沉积金属凸块; 在晶片的前表面形成第一包装层以覆盖金属凸块，同时在晶片边缘形成未覆盖的环，以露出位于两个相邻芯片之间的每个划线的端部; 稀释第一包装层以暴露金属凸块; 通过沿着未被覆盖的环的前表面上暴露的划线的两端延伸的直线切割沿着每个划线在第一包装层的前表面上形成凹槽; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 在凹陷空间中在晶片的底面沉积金属层; 切断晶片的边缘部分; 以及通过沿着沟槽切割第一包装层，晶片和金属层，从晶片分离单个芯片。