公开(公告)号：US20120298999A1

公开(公告)日：2012-11-29

申请号：US13477353

申请日：2012-05-22

申请人： Yasuhiro JINBO ,  Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Tomohiro KIMURA ,  Yoshitaka YAMAMOTO

发明人： Yasuhiro JINBO ,  Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Tomohiro KIMURA ,  Yoshitaka YAMAMOTO

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/04 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78678

摘要： An object is to reduce off-state leakage current between a source electrode and a drain electrode. One embodiment of the present invention is a semiconductor device including a gate electrode, gate insulating films and formed to cover the gate electrode, an active layer formed over the gate insulating films and located above the gate electrode, silicon layers and formed over side surfaces of the active layer and the gate insulating films, and a source electrode and a drain electrode formed over the silicon layers. The active layer is not in contact with each of the source electrode and the drain electrode.

摘要翻译： 目的是减少源极和漏电极之间的截止状态漏电流。 本发明的一个实施例是一种半导体器件，包括栅电极和栅极绝缘膜，形成为覆盖栅电极，形成在栅极绝缘膜上并位于栅电极上方的有源层，硅层并形成在 有源层和栅极绝缘膜，以及形成在硅层上的源电极和漏电极。 有源层不与源电极和漏电极中的每一个接触。

公开(公告)号：US20120298997A1

公开(公告)日：2012-11-29

申请号：US13473643

申请日：2012-05-17

申请人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Yasuhiro JINBO ,  Tomohiro KIMURA ,  Yoshitaka YAMAMOTO

发明人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Yasuhiro JINBO ,  Tomohiro KIMURA ,  Yoshitaka YAMAMOTO

IPC分类号： H01L29/786

CPC分类号： H01L29/04 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78672 ,  H01L29/78678 ,  H01L29/78696

摘要： One embodiment of the present invention is a semiconductor device which includes a gate electrode; a gate insulating film formed to cover the gate electrode; a semiconductor layer formed over the gate insulating film and placed above the gate electrode; a second insulating film formed over the semiconductor layer; a first insulating film formed over a top surface and a side surface of the second insulating film, a side surface of the semiconductor layer, and the gate insulating film; silicon layers and which are formed over the first insulating film and electrically connected to the semiconductor layer; and a source electrode and a drain electrode which are formed over the silicon layers. The source electrode and the drain electrode are electrically separated from each other over the first insulating film. The semiconductor layer is not in contact with each of the source electrode and the drain electrode.

摘要翻译： 本发明的一个实施例是包括栅电极的半导体器件; 形成为覆盖所述栅电极的栅极绝缘膜; 形成在所述栅极绝缘膜上并位于所述栅极电极上方的半导体层; 形成在所述半导体层上的第二绝缘膜; 形成在第二绝缘膜的顶表面和侧表面上的第一绝缘膜，半导体层的侧表面和栅极绝缘膜; 硅层，其形成在第一绝缘膜上并电连接到半导体层; 以及形成在硅层上的源电极和漏电极。 源电极和漏电极在第一绝缘膜上彼此电分离。 半导体层不与源电极和漏电极中的每一个接触。

公开(公告)号：US20090321743A1

公开(公告)日：2009-12-31

申请号：US12490458

申请日：2009-06-24

申请人： Toshiyuki ISA ,  Yasuhiro JINBO ,  Sachiaki TEZUKA ,  Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Shunpei YAMAZAKI

发明人： Toshiyuki ISA ,  Yasuhiro JINBO ,  Sachiaki TEZUKA ,  Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor includes, as a buffer layer, an amorphous semiconductor layer having nitrogen or an NH group between a gate insulating layer and source and drain regions and at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.

摘要翻译： 薄膜晶体管包括作为缓冲层的至少在源极和漏极区域上具有氮或NH基的非晶半导体层，栅极绝缘层与源极和漏极区之间。 与在沟道形成区域中包含非晶半导体的薄膜晶体管相比，可以提高薄膜晶体管的导通电流。 此外，与在沟道形成区域中包含微晶半导体的薄膜晶体管相比，可以减小薄膜晶体管的截止电流。

公开(公告)号：US20090142909A1

公开(公告)日：2009-06-04

申请号：US12277378

申请日：2008-11-25

申请人： Yasuhiro JINBO ,  Hidekazu MIYAIRI ,  Koji DAIRIKI

发明人： Yasuhiro JINBO ,  Hidekazu MIYAIRI ,  Koji DAIRIKI

IPC分类号： H01L21/20

CPC分类号： H01L27/127 ,  H01L21/0237 ,  H01L21/02436 ,  H01L21/02595 ,  H01L21/0262 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78696 ,  H01L31/03685 ,  H01L31/1824 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

摘要： A method for forming a microcrystalline semiconductor film over a base formed of a different material, which has high crystallinity in the entire film and at an interface with the base, is proposed. Further, a method for manufacturing a thin film transistor including a microcrystalline semiconductor film with high crystallinity is proposed. Furthermore, a method for manufacturing a photoelectric conversion device including a microcrystalline semiconductor film with high crystallinity is proposed. By forming crystal nuclei with high density and high crystallinity over a base film and then growing crystals in a semiconductor from the crystal nuclei, a microcrystalline semiconductor film which has high crystallinity at an interface with the base film, which has high crystallinity in crystal grains, and which has high adhesion between the adjacent crystal grains is formed.

摘要翻译： 提出了一种在由不同材料形成的基底上形成微晶半导体膜的方法，其在整个膜中和与基底的界面处具有高结晶度。 此外，提出了一种制造包括具有高结晶度的微晶半导体膜的薄膜晶体管的方法。 此外，提出了包括具有高结晶度的微晶半导体膜的光电转换装置的制造方法。 通过在基膜上形成具有高密度和高结晶度的晶核，然后在晶体核上生长半导体中的晶体，在晶粒中结晶度高的基膜界面处具有高结晶度的微晶半导体膜， 并且形成相邻晶粒之间具有高粘附性的材料。

公开(公告)号：US20090321737A1

公开(公告)日：2009-12-31

申请号：US12490447

申请日：2009-06-24

申请人： Toshiyuki ISA ,  Yasuhiro JINBO ,  Sachiaki TEZUKA ,  Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Shunpei YAMAZAKI ,  Takuya HIROHASHI

发明人： Toshiyuki ISA ,  Yasuhiro JINBO ,  Sachiaki TEZUKA ,  Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Shunpei YAMAZAKI ,  Takuya HIROHASHI

IPC分类号： H01L29/04

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor includes, as a buffer layer, a semiconductor layer which contains nitrogen and includes crystal regions in an amorphous structure between a gate insulating layer and source and drain regions, at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.

摘要翻译： 至少在源区和漏区侧，薄膜晶体管包括作为缓冲层的半导体层，该半导体层含有氮并且包括在栅极绝缘层和源极和漏极区之间的非晶结构中的晶体区域。 与在沟道形成区域中包含非晶半导体的薄膜晶体管相比，可以提高薄膜晶体管的导通电流。 此外，与在沟道形成区域中包含微晶半导体的薄膜晶体管相比，可以减小薄膜晶体管的截止电流。

公开(公告)号：US20090261328A1

公开(公告)日：2009-10-22

申请号：US12423123

申请日：2009-04-14

申请人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Yuji EGI ,  Yasuhiro JINBO ,  Toshiyuki ISA

发明人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Yuji EGI ,  Yasuhiro JINBO ,  Toshiyuki ISA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288 ,  C23C16/0272 ,  C23C16/24 ,  C23C16/4404 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： Disclosed is a thin film transistor which includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which functions as a channel formation region; and a semiconductor layer including an impurity element imparting one conductivity type. The semiconductor layer exists in a state that a plurality of crystalline particles is dispersed in an amorphous silicon and that the crystalline particles have an inverted conical or inverted pyramidal shape. The crystalline particles grow approximately radially in a direction in which the semiconductor layer is deposited. Vertexes of the inverted conical or inverted pyramidal crystal particles are located apart from an interface between the gate insulating layer and the semiconductor layer.

摘要翻译： 公开了一种薄膜晶体管，其在具有绝缘表面的衬底上方包括覆盖栅电极的栅绝缘层; 用作沟道形成区域的半导体层; 以及包含赋予一种导电型的杂质元素的半导体层。 半导体层以多个结晶粒子分散在非晶硅中的状态存在，并且结晶粒子具有倒锥形或倒棱锥形状。 晶体颗粒沿半导体层沉积的方向大致径向生长。 倒锥形或倒锥形晶体颗粒的顶点位于与栅极绝缘层和半导体层之间的界面之外。

公开(公告)号：US20100096631A1

公开(公告)日：2010-04-22

申请号：US12423111

申请日：2009-04-14

申请人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Yuji EGI ,  Yasuhiro JINBO ,  Toshiyuki ISA

发明人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Yuji EGI ,  Yasuhiro JINBO ,  Toshiyuki ISA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： A thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which includes a plurality of crystalline regions in an amorphous structure and which forms a channel formation region, in contact with the gate insulating layer; a semiconductor layer including an impurity element imparting one conductivity type, which forms source and drain regions; and a buffer layer including an amorphous semiconductor between the semiconductor layer and the semiconductor layer including an impurity element imparting one conductivity type. The crystalline regions have an inverted conical or inverted pyramidal crystal particle which grows approximately radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer.

摘要翻译： 薄膜晶体管包括在具有绝缘表面的衬底上，覆盖栅电极的栅绝缘层; 半导体层，其包括与所述栅极绝缘层接触的非晶结构中的多个结晶区域，并形成沟道形成区域; 包含赋予一种导电类型的杂质元素的半导体层，其形成源区和漏区; 以及包括在半导体层和半导体层之间的非晶半导体的缓冲层，其包括赋予一种导电类型的杂质元素。 晶体区域具有从远离栅极绝缘层和半导体层之间的界面的位置沿着沉积半导体层的方向大致径向生长的倒锥形或倒棱锥晶体颗粒。

公开(公告)号：US20120100675A1

公开(公告)日：2012-04-26

申请号：US13267257

申请日：2011-10-06

申请人： Ryu KOMATSU ,  Yasuhiro JINBO ,  Hidekazu MIYAIRI ,  Yoshitaka YAMAMOTO

发明人： Ryu KOMATSU ,  Yasuhiro JINBO ,  Hidekazu MIYAIRI ,  Yoshitaka YAMAMOTO

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L29/78696 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/28008 ,  H01L29/04 ,  H01L29/6675

摘要： To provide a manufacturing method of a microcrystalline silicon film having both high crystallinity and high film density. In the manufacturing method of a microcrystalline silicon film according to the present invention, a first microcrystalline silicon film that includes mixed phase grains is formed over an insulating film under a first condition, and a second microcrystalline silicon film is formed thereover under a second condition. The first condition and the second condition are a condition in which a deposition gas containing silicon and a gas containing hydrogen are used as a first source gas and a second source gas. The first source gas is supplied under the first condition in such a manner that supply of a first gas and supply of a second gas are alternately performed.

摘要翻译： 提供具有高结晶度和高膜密度的微晶硅膜的制造方法。 在本发明的微晶硅膜的制造方法中，在第一条件下，在绝缘膜上形成包含混晶相的第一微晶硅膜，在第二条件下形成第二微晶硅膜。 第一条件和第二条件是使用含硅和含氢气体的沉积气体作为第一源气体和第二源气体的条件。 在第一条件下以第一气体的供给和第二气体的供给交替进行的方式供给第一源气体。

公开(公告)号：US20120299006A1

公开(公告)日：2012-11-29

申请号：US13477373

申请日：2012-05-22

申请人： Hidekazu MIYAIRI ,  Atsushi HIROSE ,  Yoshitaka YAMAMOTO ,  Tomohiro KIMURA

发明人： Hidekazu MIYAIRI ,  Atsushi HIROSE ,  Yoshitaka YAMAMOTO ,  Tomohiro KIMURA

IPC分类号： H01L27/06

CPC分类号： H01L29/78696 ,  H01L29/04 ,  H01L29/78633 ,  H01L29/78648

摘要： An object is to prevent light leakage caused due to misregistration even when the width of a black matrix layer is not expanded to a designed value or larger. One embodiment of the present invention is a semiconductor device including a single-gate thin film transistor in which a first semiconductor layer is sandwiched between a bottom-gate electrode and a first black matrix layer. The first semiconductor layer and the first black matrix layer overlap with each other.

摘要翻译： 目的是防止黑色矩阵层的宽度未扩大到设计值以上的情况下由于配准不良引起的漏光。 本发明的一个实施例是一种包括单栅极薄膜晶体管的半导体器件，其中第一半导体层夹在底栅电极和第一黑矩阵层之间。 第一半导体层和第一黑矩阵层彼此重叠。

公开(公告)号：US20120299074A1

公开(公告)日：2012-11-29

申请号：US13477334

申请日：2012-05-22

申请人： Atsushi HIROSE ,  Hidekazu MIYAIRI ,  Yoshitaka YAMAMOTO ,  Tomohiro KIMURA

发明人： Atsushi HIROSE ,  Hidekazu MIYAIRI ,  Yoshitaka YAMAMOTO ,  Tomohiro KIMURA

IPC分类号： H01L27/06

CPC分类号： H01L29/78633 ,  H01L29/78648

摘要： A semiconductor device in which light leakage due to misalignment is prevented even when a black matrix layer is not expanded to a designed value or more is provided. In a semiconductor device including a dual-gate thin film transistor in which a semiconductor layer is sandwiched between a bottom gate electrode and a top gate electrode, the top gate electrode is formed of a first black matrix layer, and the top gate electrode overlaps with the semiconductor layer.

摘要翻译： 即使黑矩阵层不扩展到设计值以上，也能够防止由于未对准而导致的漏光的半导体装置。 在包括半导体层夹在底栅电极和顶栅电极之间的双栅极薄膜晶体管的半导体器件中，顶栅电极由第一黑矩阵层形成，顶栅电极与 半导体层。