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43 条记录 (耗时 0.013 秒)

    Method of Filling Large Deep Trench with High Quality Oxide for Semiconductor Devices
    6.
    发明申请
    Method of Filling Large Deep Trench with High Quality Oxide for Semiconductor Devices 有权
    用于半导体器件的高质量氧化物填充大深沟槽的方法

    公开(公告)号：US20110140228A1

    公开(公告)日：2011-06-16

    申请号：US12637988

    申请日：2009-12-15

    申请人： Xiaobin Wang ,  Anup Bhalla ,  Yeeheng Lee

    发明人： Xiaobin Wang ,  Anup Bhalla ,  Yeeheng Lee

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L29/0657 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76227 ,  H01L29/407 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

    摘要翻译： 公开了一种用于产生具有沟槽尺寸TCS和沟槽深度TCD的具有氧化物填充的大深沟槽（OFLDT）部分的半导体器件结构的方法。 体积半导体层（BSL）设置有厚度BSLT> TCD。 一个大的沟槽顶部区域（LTTA）映射到BSL顶部，其几何形状等于OFLDT。 LTTA被划分为散置的，互补的临时区域ITA-A和ITA-B。 通过去除对应于ITA-B的散装半导体材料，在顶部BSL表面上形成了许多深度TCD的临时垂直沟槽。 对应于ITA-A的剩余体积半导体材料被转化为氧化物。 如果在经过转换的ITA-A之间仍然留有剩余空间，则剩余空间被氧化物沉积填满。 重要的是，所有ITA-A和ITA-B的几何形状都应该被简单而小型化，以便于快速有效地进行氧化物转换和氧化物填充。

    Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions
    7.
    发明申请
    Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions 有权
    用于制造具有沟槽氧化物 - 纳米管超结的器件的配置和方法

    公开(公告)号：US20100314682A1

    公开(公告)日：2010-12-16

    申请号：US12661004

    申请日：2010-03-05

    申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

    发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762

    CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

    摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

    摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

    Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions
    10.
    发明授权
    Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions 有权
    用于制造具有沟槽氧化物 - 纳米管超结的器件的配置和方法

    公开(公告)号：US08390058B2

    公开(公告)日：2013-03-05

    申请号：US12661004

    申请日：2010-03-05

    申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

    发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

    摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

    摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。