公开(公告)号：US08890738B2

公开(公告)日：2014-11-18

申请号：US14110192

申请日：2012-04-04

申请人： Tae Wook Kim ,  Yeomyung Kim ,  Gunhee Han

发明人： Tae Wook Kim ,  Yeomyung Kim ,  Gunhee Han

IPC分类号： H03M1/12 ,  G04F10/00 ,  H03M1/00 ,  H04L7/033

CPC分类号： G04F10/005 ,  G04F10/00 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M2201/4233 ,  H04L7/033

摘要： The present disclosure provides a time-to-digital (TDC) converter, comprising: a coarse TDC receiving a start signal and a stop signal, delaying the first start signal in a first time unit to generate n first delayed start signals (where n is an integer equal to or larger than 2), measuring a time difference between the first delayed start signal and the stop signal in the first time unit, and generating second delayed start signals that are obtained by delaying the first delayed start signals in a time unit shorter than the first time unit; and a fine TDC receiving and delaying the second delayed start signal generated from the coarse TDC and receiving the stop signal, and measuring a time difference between the second delayed start signal and the stop signal in a second time unit.

摘要翻译： 本公开提供了一种时间数字（TDC）转换器，包括：粗TDC接收起始信号和停止信号，以第一时间单位延迟第一起始信号以产生n个第一延迟起始信号（其中n为 等于或大于2的整数），测量第一时间单位中第一延迟起始信号和停止信号之间的时间差，以及产生通过以时间单位延迟第一延迟开始信号而获得的第二延迟起始信号 比第一时间单位短; 以及精细TDC，接收并延迟从粗TDC产生的第二延迟开始信号并接收停止信号，并且以第二时间单位测量第二延迟开始信号和停止信号之间的时间差。

公开(公告)号：US20140292552A1

公开(公告)日：2014-10-02

申请号：US14110192

申请日：2012-04-04

申请人： Tae Wook Kim ,  Yeomyung Kim ,  Gunhee Han

发明人： Tae Wook Kim ,  Yeomyung Kim ,  Gunhee Han

IPC分类号： G04F10/00

CPC分类号： G04F10/005 ,  G04F10/00 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M2201/4233 ,  H04L7/033

摘要： The present disclosure provides a time-to-digital (TDC) converter, comprising: a coarse TDC receiving a start signal and a stop signal, delaying the first start signal in a first time unit to generate n first delayed start signals (where n is an integer equal to or larger than 2), measuring a time difference between the first delayed start signal and the stop signal in the first time unit, and generating second delayed start signals that are obtained by delaying the first delayed start signals in a time unit shorter than the first time unit; and a fine TDC receiving and delaying the second delayed start signal generated from the coarse TDC and receiving the stop signal, and measuring a time difference between the second delayed start signal and the stop signal in a second time unit.

摘要翻译： 本公开提供了一种时间数字（TDC）转换器，包括：粗TDC接收起始信号和停止信号，以第一时间单位延迟第一起始信号以产生n个第一延迟起始信号（其中n为 等于或大于2的整数），测量第一时间单位中第一延迟起始信号和停止信号之间的时间差，以及产生通过以时间单位延迟第一延迟开始信号而获得的第二延迟起始信号 比第一时间单位短; 以及精细TDC，接收并延迟从粗TDC产生的第二延迟开始信号并接收停止信号，并且以第二时间单位测量第二延迟开始信号和停止信号之间的时间差。

公开(公告)号：US08362933B2

公开(公告)日：2013-01-29

申请号：US13083698

申请日：2011-04-11

申请人： Yeomyung Kim ,  Tae Wook Kim

发明人： Yeomyung Kim ,  Tae Wook Kim

IPC分类号： H03M1/48

CPC分类号： G04F10/005

摘要： Provided are a TDC having a pipeline or cyclic structure and an operating method thereof. The TDC includes a first stage block and a second stage block. The first stage block detects a first bit of a digital code for a time difference between first and second input signals. The second stage block detects a second bit of the digital code for a time difference between first and second output signals of the first stage block. The first stage block amplifies a time difference between first and second delay signals for the first and second input signals to generate the first and second output signals, and transfers the first and second output signals to the second stage block.

摘要翻译： 提供具有流水线或循环结构的TDC及其操作方法。 TDC包括第一级块和第二级块。 第一级块检测第一和第二输入信号之间的时间差的数字代码的第一位。 第二级块检测第一级块的第一和第二输出信号之间的时间差的数字代码的第二位。 第一级块放大第一和第二输入信号的第一和第二延迟信号之间的时间差，以产生第一和第二输出信号，并将第一和第二输出信号传送到第二级块。

公开(公告)号：US20130101114A1

公开(公告)日：2013-04-25

申请号：US13806628

申请日：2011-01-28

申请人： Dong Kyue Kim ,  Byong Deok Choi ,  Tae Wook Kim

发明人： Dong Kyue Kim ,  Byong Deok Choi ,  Tae Wook Kim

IPC分类号： G06F21/60

CPC分类号： G06F21/73 ,  G06F7/588 ,  G06F21/602 ,  G06F21/70 ,  G06F21/86 ,  G09C1/00 ,  H04L9/0861 ,  H04L9/0866

摘要： Provided is an apparatus for generating an identification key by a probabilistic determination of a short occurring between nodes constituting a circuit, by violating a design rule provided during a semiconductor manufacturing process. The identification key generating apparatus may include an identification key generator to generate an identification key based on whether a contact or a via used to electrically connect conductive layers in a semiconductor chip shorts the conductive layers, and an identification key reader to read the identification key by reading whether the contact or the via shorts the conductive layers.

摘要翻译： 提供了一种用于通过违反在半导体制造过程中提供的设计规则，通过概略确定构成电路的节点之间的短路来生成识别密钥的装置。 识别密钥生成装置可以包括识别密钥生成器，其基于用于电连接半导体芯片中的导电层的接触或通路是否使导电层短路来产生识别密钥，以及识别密钥读取器，通过以下方式读取识别密钥： 读取接触或通孔是否使导电层短路。

公开(公告)号：US08237509B2

公开(公告)日：2012-08-07

申请号：US11852946

申请日：2007-09-10

申请人： Tae Wook Kim ,  Guy Klemens ,  Kenneth Charles Barnett ,  Susanta Sangupta ,  Gurkanwal Singh Sahota

发明人： Tae Wook Kim ,  Guy Klemens ,  Kenneth Charles Barnett ,  Susanta Sangupta ,  Gurkanwal Singh Sahota

IPC分类号： H03F3/04

CPC分类号： H03F1/223 ,  H03F3/195 ,  H03F3/45188 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/168 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45034 ,  H03F2203/45058 ,  H03F2203/45138 ,  H03F2203/45296 ,  H03F2203/45301 ,  H03F2203/45316 ,  H03F2203/45396 ,  H03F2203/7239 ,  H03G1/0017 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/3052 ,  H03G3/3078

摘要： An amplifier with integrated filter (e.g., an LNA) is described. In one design, the amplifier may include a gain stage, a filter stage, and a buffer stage. The gain stage may provide signal amplification for an input signal. The filter stage may provide filtering for the input signal. The buffer stage may buffer a filtered signal from the filter stage. The amplifier may further include a second filter stage and a second buffer stage. The second filter stage may provide additional filtering for the input signal. The second buffer stage may buffer a second filtered signal from the second filter stage. All of the stages may be stacked and coupled between a supply voltage and circuit ground. The filter stage(s) may implement an elliptical lowpass filter. Each filter stage may include an inductor and a capacitor coupled in parallel and forming a resonator tank to attenuate interfering signals.

摘要翻译： 描述了具有集成滤波器（例如，LNA）的放大器。 在一种设计中，放大器可以包括增益级，滤波级和缓冲级。 增益级可以为输入信号提供信号放大。 滤波器级可以为输入信号提供滤波。 缓冲级可以缓冲来自滤波级的滤波信号。 放大器还可以包括第二滤波器级和第二缓冲级。 第二滤波器级可以为输入信号提供额外的滤波。 第二缓冲级可以缓冲来自第二滤波级的第二滤波信号。 所有级可以堆叠并耦合在电源电压和电路接地之间。 滤波器级可以实现椭圆形低通滤波器。 每个滤波器级可以包括并联耦合的电感器和电容器，并形成谐振器箱以衰减干扰信号。

公开(公告)号：US07602227B2

公开(公告)日：2009-10-13

申请号：US11128351

申请日：2005-05-13

申请人： Tae Wook Kim ,  Bonkee Kim ,  Kwyro Lee

发明人： Tae Wook Kim ,  Bonkee Kim ,  Kwyro Lee

IPC分类号： G06G7/12

CPC分类号： H03D7/1441 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0043 ,  H03D2200/0047 ,  H03F1/3211 ,  H03F3/45183

摘要： The present invention relates to a differential amplifier and a mixer for improving the linearity. The differential amplifier circuit according to this present invention, includes first and second load stages each having a predetermined voltage value, a main differential amplifier unit having a first differential stage that forms a differential pair in such a way as to amplify a difference between a first input voltage and a second input voltage, and a constant current source, which has a predetermined current driving capability and is connected serially between a power source voltage terminal and a ground terminal, and a auxiliary differential amplifier unit having a second differential stage that forms a differential pair in such a way as to amplify a difference between a third input voltage and a fourth input voltage connected between the first load stage and a second load stage, and the ground, respectively.

摘要翻译： 本发明涉及一种用于提高线性度的差分放大器和混频器。 根据本发明的差分放大器电路包括各自具有预定电压值的第一和第二负载级，主差分放大器单元具有形成差分对的第一差分级，以便放大第一和第二负载级之间的差异 输入电压和第二输入电压，以及恒定电流源，其具有预定的电流驱动能力并且串联地连接在电源电压端子和接地端子之间;以及辅助差分放大器单元，具有形成第二差分级的辅助差分放大器单元 差分对以分别放大连接在第一负载级与第二负载级之间的第三输入电压与第四输入电压之间的差的方式和地。

公开(公告)号：US20080220735A1

公开(公告)日：2008-09-11

申请号：US11684120

申请日：2007-03-09

申请人： Tae Wook Kim ,  Kenneth Charles Barnett

发明人： Tae Wook Kim ,  Kenneth Charles Barnett

IPC分类号： H04B1/18

CPC分类号： H03F1/56 ,  H03F3/45188 ,  H03F2203/45296 ,  H03F2203/45316 ,  H03F2203/45511 ,  H03F2203/45512 ,  H03F2203/45704 ,  H03H11/1291

摘要： This disclosure is directed to a frequency-selective low noise amplifier (LNA) with wide-band impedance and noise matching. The LNAS may include a closed loop circuit that supports wideband input matching. For example, the closed loop circuit may be configure to impedance match an input signal and provide a low noise figure. In addition, the LNA may include an open loop circuit that amplifies the input signal and provides a high output impedance. The open loop circuit may further include a selectivity filter that filters out frequencies outside a desired frequency band. The LNA may drive a tunable band-pass filter via the open loop circuit.

摘要翻译： 本公开涉及具有宽带阻抗和噪声匹配的频率选择性低噪声放大器（LNA）。 LNAS可以包括支持宽带输入匹配的闭环电路。 例如，闭环电路可以被配置为阻抗匹配输入信号并提供低噪声系数。 此外，LNA可以包括放大输入信号并提供高输出阻抗的开环电路。 开环电路还可以包括滤除期望频带外的频率的选择性滤波器。 LNA可以通过开环电路驱动可调谐带通滤波器。

公开(公告)号：US20080204148A1

公开(公告)日：2008-08-28

申请号：US11852946

申请日：2007-09-10

申请人： Tae Wook Kim ,  Guy Klemens ,  Kenneth Charles Barnett ,  Susanta Sangupta ,  Gurkanwal Singh Sahota

发明人： Tae Wook Kim ,  Guy Klemens ,  Kenneth Charles Barnett ,  Susanta Sangupta ,  Gurkanwal Singh Sahota

IPC分类号： H03F3/187

CPC分类号： H03F1/223 ,  H03F3/195 ,  H03F3/45188 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/168 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45034 ,  H03F2203/45058 ,  H03F2203/45138 ,  H03F2203/45296 ,  H03F2203/45301 ,  H03F2203/45316 ,  H03F2203/45396 ,  H03F2203/7239 ,  H03G1/0017 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/3052 ,  H03G3/3078

摘要： An amplifier with integrated filter (e.g., an LNA) is described. In one design, the amplifier may include a gain stage, a filter stage, and a buffer stage. The gain stage may provide signal amplification for an input signal. The filter stage may provide filtering for the input signal. The buffer stage may buffer a filtered signal from the filter stage. The amplifier may further include a second filter stage and a second buffer stage. The second filter stage may provide additional filtering for the input signal. The second buffer stage may buffer a second filtered signal from the second filter stage. All of the stages may be stacked and coupled between a supply voltage and circuit ground. The filter stage(s) may implement an elliptical lowpass filter. Each filter stage may include an inductor and a capacitor coupled in parallel and forming a resonator tank to attenuate interfering signals.

摘要翻译： 描述了具有集成滤波器（例如，LNA）的放大器。 在一种设计中，放大器可以包括增益级，滤波级和缓冲级。 增益级可以为输入信号提供信号放大。 滤波器级可以为输入信号提供滤波。 缓冲级可以缓冲来自滤波级的滤波信号。 放大器还可以包括第二滤波器级和第二缓冲级。 第二滤波器级可以为输入信号提供额外的滤波。 第二缓冲级可以缓冲来自第二滤波级的第二滤波信号。 所有级可以堆叠并耦合在电源电压和电路接地之间。 滤波器级可以实现椭圆形低通滤波器。 每个滤波器级可以包括并联耦合的电感器和电容器，并形成谐振器箱以衰减干扰信号。

公开(公告)号：US07408411B2

公开(公告)日：2008-08-05

申请号：US11201429

申请日：2005-08-11

申请人： Tae Wook Kim ,  Bonkee Kim ,  Kwyro Lee

发明人： Tae Wook Kim ,  Bonkee Kim ,  Kwyro Lee

IPC分类号： H03G3/00

CPC分类号： H03G1/0088

摘要： Disclosed is a high linearity programmable gain amplifier using a switch, including an attenuating portion for controlling a gain of a signal and an amplifying portion having a first amplifying part and a second amplifying part, for amplifying an input signal and outputting a signal amplified, wherein the first amplifying part has a first amplifier for amplifying an input signal and a first switch for activating the first amplifier and the second amplifying part has a second amplifier for amplifying an input signal and a second switch for activating the second amplifier.

摘要翻译： 公开了一种使用开关的高线性可编程增益放大器，包括用于控制信号增益的衰减部分和具有第一放大部分和第二放大部分的放大部分，用于放大输入信号并输出​​放大的信号，其中 第一放大部分具有用于放大输入信号的第一放大器和用于激活第一放大器的第一开关，第二放大部分具有用于放大输入信号的第二放大器和用于启动第二放大器的第二开关。

公开(公告)号：US06933779B2

公开(公告)日：2005-08-23

申请号：US10633589

申请日：2003-08-05

申请人： Kwyro Lee ,  Tae Wook Kim

发明人： Kwyro Lee ,  Tae Wook Kim

IPC分类号： H03F1/26 ,  H03F3/72 ,  H03G1/00 ,  H03F1/14 ,  H03F3/191 ,  H03G3/30

CPC分类号： H03G1/0088 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/7236

摘要： The present invention is related to a variable gain low noise amplifier that optimizes input matching, gain and noise characteristics, and linearity. The variable gain low noise amplifier according to an embodiment of the present invention includes a first amplifying cell that operates in a high gain mode, a second amplifying cell that operates in a low gain mode, a selectively matching circuit, and a first short-circuit means. The variable gain low noise amplifier according to the present invention selects the best operation in each gain mode so that the circuit operated in high and low gain modes does not affect a load of another circuit.

摘要翻译： 本发明涉及优化输入匹配，增益和噪声特性以及线性度的可变增益低噪声放大器。 根据本发明实施例的可变增益低噪声放大器包括以高增益模式操作的第一放大单元，以低增益模式操作的第二放大单元，选择性匹配电路和第一短路 手段。 根据本发明的可变增益低噪声放大器在每个增益模式中选择最佳操作，使得以高和低增益模式操作的电路不影响另一电路的负载。