公开(公告)号：US20050009367A1

公开(公告)日：2005-01-13

申请号：US10615744

申请日：2003-07-09

申请人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Szu-An Wu ,  Ying-Lang Wang ,  Pei-Fen Chou

发明人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Szu-An Wu ,  Ying-Lang Wang ,  Pei-Fen Chou

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/76 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02131 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/76837

摘要： A method of forming an FSG film comprising the following steps. A structure is provided. An FSG film is formed over the structure by an HDP-CVD process under the following conditions: no Argon (Ar)—side sputter; SiF4 flow: from about 53 to 63 sccm; an N2 flow: from about 25 to 35 sccm; and an RF power to provide a uniform plasma density.

摘要翻译： 一种形成FSG膜的方法，包括以下步骤。 提供了一种结构。 在以下条件下通过HDP-CVD工艺在该结构上形成FSG膜：无氩（Ar）侧溅射; SiF4流量：约53至63sccm; N2流量：约25至35sccm; 和RF功率以提供均匀的等离子体密度。

公开(公告)号：US06602560B2

公开(公告)日：2003-08-05

申请号：US10196850

申请日：2002-07-16

申请人： Yi-Lung Cheng ,  Wen-Kung Cheng ,  Ming-Hwa Yoo ,  Szu-An Wu ,  Ying-Long Wang ,  Pei-Fen Chou

发明人： Yi-Lung Cheng ,  Wen-Kung Cheng ,  Ming-Hwa Yoo ,  Szu-An Wu ,  Ying-Long Wang ,  Pei-Fen Chou

IPC分类号： C23C1640

CPC分类号： C23C16/4405 ,  B08B7/0035

摘要： A method of removing residual fluorine present in a HDP-CVD chamber which includes a high pressure seasoning process, a dry-cleaning process, and a low-pressure deposition process.

摘要翻译： 一种除去存在于HDP-CVD室中的残余氟的方法，其包括高压调味处理，干洗处理和低压沉积工艺。

公开(公告)号：US06479098B1

公开(公告)日：2002-11-12

申请号：US09747135

申请日：2000-12-26

申请人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C1640

CPC分类号： H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

摘要翻译： 一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。 腔室等离子体处理区域部件被清洁。 然后如下调节室。 在室等离子体处理区域部件上形成第一USG层。 在第一USG层上形成FSG层。 在FSG层上形成第二个USG层。 其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

公开(公告)号：US06815072B2

公开(公告)日：2004-11-09

申请号：US10256714

申请日：2002-09-27

申请人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： B05C1100

CPC分类号： H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

公开(公告)号：US06815007B1

公开(公告)日：2004-11-09

申请号：US10086258

申请日：2002-03-04

申请人： Ming-Hwa Yoo ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C1622

CPC分类号： H01J37/32862 ,  C23C16/308 ,  C23C16/401 ,  C23C16/4404 ,  H01J2237/022

摘要： A method for reducing contaminants in a processing chamber having an inner wall by seasoning the walls. The method comprising the following steps. A first USG film is formed over the processing chamber inner wall. An FSG film is formed over the first USG film. A second USG film is formed over the FSG film. A nitrogen-containing film is formed over the second USG film wherein the first USG film, the FSG film, the second USG film and the nitrogen-containing film comprise a UFUN season film.

公开(公告)号：US06802935B2

公开(公告)日：2004-10-12

申请号：US10103618

申请日：2002-03-21

申请人： Yi-Lung Cheng ,  Hui-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Yi-Lung Cheng ,  Hui-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： B65G4907

CPC分类号： H01L21/67167 ,  C23C16/4405 ,  C23C16/54 ,  H01L21/67196 ,  Y10S414/135

摘要： A semiconductor processing apparatus and method are disclosed herein, including a plurality of process chambers, wherein at least one semiconductor processing operation occurs within each process chamber among the plurality of process chambers. Additionally, the apparatus and method disclosed herein include a robot mechanism for rotating each process chamber among the plurality of process chambers upon completion of an associated semiconductor processing operation. Such a robot mechanism may comprise a plurality of robots. Specifically, such a plurality of robots may include six robots configured on an associated carousel.

摘要翻译： 本文公开了包括多个处理室的半导体处理装置和方法，其中在多个处理室中的每个处理室内发生至少一个半导体处理操作。 此外，本文公开的装置和方法包括机器人机构，用于在完成相关联的半导体处理操作时在多个处理室中旋转每个处理室。 这样的机器人机构可以包括多个机器人。 具体地说，这样的多个机器人可以包括配置在相关转盘上的六个机器人。

公开(公告)号：US20060166458A1

公开(公告)日：2006-07-27

申请号：US11044814

申请日：2005-01-26

申请人： Yi-Lung Cheng ,  Szu-An Wu ,  Yi-Lang Wang

发明人： Yi-Lung Cheng ,  Szu-An Wu ,  Yi-Lang Wang

IPC分类号： H01L21/76 ,  H01L21/461

CPC分类号： H01L21/31053 ,  H01L21/76224

摘要： A shallow trench isolation (STI) structure for semiconductor devices is formed using a deposited silicon layer formed over a polish stop layer formed over an oxide formed on a substrate. The polish stop layer may be nitride. An opening is formed extending through the deposited silicon layer and the nitride and oxide layers and extending into the substrate. A deposited oxide is formed filling the opening and extending over the top surface of deposited silicon layer. A chemical mechanical polishing operation polishes the deposited silicon layer at a rate faster than the deposited oxide layer to produce an STI with a convex portion extending above the nitride layer. Dishing problems are avoided and the structure may be subsequently planarized.

摘要翻译： 用于半导体器件的浅沟槽隔离（STI）结构使用形成在形成在衬底上的氧化物上形成的抛光停止层上的沉积硅层形成。 抛光停止层可以是氮化物。 形成延伸穿过沉积的硅层和氮化物和氧化物层并延伸到衬底中的开口。 形成沉积氧化物，填充开口并在沉积的硅层的顶表面上延伸。 化学机械抛光操作以比沉积的氧化物层更快的速率抛光沉积的硅层，以产生具有在氮化物层上方延伸的凸部的STI。 避免了抛光问题，并且可以随后平面化该结构。

公开(公告)号：US20050121751A1

公开(公告)日：2005-06-09

申请号：US10729217

申请日：2003-12-04

申请人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

发明人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/76 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/5329 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

公开(公告)号：US06979656B2

公开(公告)日：2005-12-27

申请号：US10729217

申请日：2003-12-04

申请人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

发明人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/76 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/5329 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

摘要翻译： 制造电介质层的方法提供了当形成碳和卤素掺杂的硅酸盐玻璃介电层时与卤素源材料分开的碳源材料的使用。 当形成碳和卤素掺杂的硅酸盐玻璃介电层时，使用单独的碳和卤素源材料提供了增强的工艺自由度。 具有大于约3.0的介电常数的这种碳和卤素掺杂的硅酸盐玻璃介电层特别适用于镶嵌法中的本征平面化停止层。 包含碳和卤素掺杂的硅酸盐玻璃的双层电介质层结构和不含卤素掺杂的碳掺杂的硅酸盐玻璃介电层在双镶嵌方法中是有用的。

公开(公告)号：US06703317B1

公开(公告)日：2004-03-09

申请号：US10356248

申请日：2003-01-30

申请人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Sze-An Wu ,  Ying-Lung Wang

发明人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Sze-An Wu ,  Ying-Lung Wang

IPC分类号： H01L21302

CPC分类号： H01L21/3105 ,  H01L21/02052 ,  H01L21/76826 ,  H01L21/76837 ,  Y10S438/906

摘要： A method of reducing an electrical charge imbalance on a wafer process surface including providing a semiconductor wafer having a process surface including an upper most first material layer; cleaning the process surface according to a wafer cleaning process including at least one of spraying and scrubbing to produce an electrical charge imbalance at the process surface; and, subjecting the process surface to a nitrogen containing plasma treatment to at least partially neutralize the electrical charge imbalance.

摘要翻译： 一种减少晶片工艺表面上的电荷不平衡的方法，包括提供具有包括最上面的第一材料层的工艺表面的半导体晶片; 根据包括喷射和洗涤中的至少一种的晶片清洁过程清洁工艺表面以在工艺表面产生电荷不平衡; 并且使所述工艺表面进行含氮等离子体处理以至少部分地中和所述电荷不平衡。