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1.发明授权Process for fabricating nonvolatile random access memory having a tunnel oxide film 失效制造具有隧道氧化膜的非挥发性随机存取存储器的方法
公开(公告)号：US5411904A
公开(公告)日：1995-05-02
申请号：US231740
申请日：1994-04-25
IPC分类号： H01L21/8247 , H01L21/266
CPC分类号： H01L27/11521 , H01L27/11524 , Y10S438/981
摘要： A nonvolatile random access memory comprising a nonvolatile random access memory unit having on a substrate an EEPROM having a tunnel oxide film and a floating gate, and a DRAM linked to the EEPROM, a thermal oxide film being selectively formed between the EEPROM and another EEPROM adjacent thereto, the tunnel regions of the respective EEPROMs being provided as self-aligned with the respective ends of the thermal oxide film and positioned at the respective ends of an impurity ion implantation pattern for use in forming a source region of the EEPROMs.
摘要翻译： 一种非易失性随机存取存储器，包括在衬底上具有隧道氧化物膜和浮动栅极的EEPROM和与EEPROM连接的DRAM的非易失性随机存取存储器单元，选择性地形成在EEPROM和另一个EEPROM之间的热氧化膜 各个EEPROM的隧道区域被设置为与热氧化膜的相应端部自对准并且位于用于形成EEPROM的源极区域的杂质离子注入图案的各个端部。
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公开(公告)号：US5401993A
公开(公告)日：1995-03-28
申请号：US083873
申请日：1993-06-30
IPC分类号： H01L21/8247 , G11C17/16 , H01L21/8246 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , H01L27/02 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： G11C17/16 , H01L27/112 , H01L27/115
摘要： A non-volatile memory includes a single transistor having a semiconductor substrate, source and drain diffusion layers formed on a surface of the semiconductor substrate, and a gate electrode provided on the semiconductor substrate with a gate insulating film interposed between them. The non-volatile memory further includes a programmable insulating film provided in self-alignment between the gate electrode and at least one of the source and drain diffusion layers and the programmable insulating film is broken down by a voltage applied to the gate electrode so as to execute programming.
摘要翻译： 非易失性存储器包括具有半导体衬底的单晶体管，形成在半导体衬底的表面上的源极和漏极扩散层，以及设置在半导体衬底上的栅电极，栅极绝缘膜置于它们之间。 非易失性存储器还包括设置在栅极电极和源极和漏极扩散层中的至少一个之间自对准的可编程绝缘膜，并且可编程绝缘膜被施加到栅电极的电压分解，从而 执行编程。
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公开(公告)号：US5139964A
公开(公告)日：1992-08-18
申请号：US646203
申请日：1991-01-28
IPC分类号： H01L21/76 , H01L21/308 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/3085 , H01L21/32 , H01L21/7621 , Y10S438/944
摘要： An improved LOCOS method for forming an isolation region with a higher breakdown voltage and a reduced width in a semiconductor device, comprising the steps of:(a) forming on a silicon substrate a silicon nitride layer having a predetermined pattern and a tapered-slant side wall, between the silicon nitride layer and the silicon substrate being formed a silicon oxide layer,(b) subjecting the silicon substrate to an isotropic etching using the silicon nitride layer as a mask to form a recess on the substrate, the recess extending to and under the side wall of the silicon nitride layer, and(c) forming a channel stopper region by implanting an impurity into the silicon substrate through the recess-formed surface, and thereafter growing and forming a LOCOS layer on the recess-formed surface to obtain an isolation region.
摘要翻译： 一种用于在半导体器件中形成具有较高击穿电压和减小的宽度的隔离区域的改进的LOCOS方法，包括以下步骤：（a）在硅衬底上形成具有预定图案和倾斜斜面的氮化硅层 在氮化硅层和硅衬底之间形成硅氧化物层，（b）使用氮化硅层作为掩模对硅衬底进行各向同性蚀刻，以在衬底上形成凹部， 在氮化硅层的侧壁下方，（c）通过凹陷形成表面向硅衬底中注入杂质形成通道阻挡区域，然后在凹形形成表面上生长并形成LOCOS层以获得 隔离区。
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公开(公告)号：US5108783A
公开(公告)日：1992-04-28
申请号：US454368
申请日：1989-12-21
申请人： Makoto Tanigawa , Hidehisa Tateoka , Keizo Sakiyama , Shigeo Ohnishi , Yoshimitsu Yamauchi , Kenichi Tanaka
发明人： Makoto Tanigawa , Hidehisa Tateoka , Keizo Sakiyama , Shigeo Ohnishi , Yoshimitsu Yamauchi , Kenichi Tanaka
IPC分类号： H01L21/76 , H01L21/08 , H01L21/74 , H01L21/762 , H01L21/763 , H01L27/08
CPC分类号： H01L21/763 , H01L21/74 , H01L21/76202 , H01L21/76237
摘要： A process for producing a semiconductor device including the steps of:(a) forming a trench in a semiconductor substrate at a portion thereof where an isolating zone is to be formed,(b) doping the substrate with an impurity element from the inner wall thereof defining the trench to form a high-concentration impurity diffused region, and(c) etching the bottom surface of the trench to increase the depth of the trench, thereby separating the impurity diffused region to form the isolating zone,which is useful for the fabrication of semiconductor devices of high integration with low well resistance.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：（a）在半导体衬底的形成隔离区的部分形成沟槽，（b）从其内壁掺杂杂质元素的衬底 限定沟槽以形成高浓度杂质扩散区域，以及（c）蚀刻沟槽的底表面以增加沟槽的深度，由此分离杂质扩散区域以形成隔离区，其可用于制造 的半导体器件，具有低阱电阻的高集成度。
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5.发明授权Semiconductor memory device having a volatile memory device and a non-volatile memory device 失效具有易失性存储器件和非易失性存储器件的半导体存储器件
公开(公告)号：US5075888A
公开(公告)日：1991-12-24
申请号：US308854
申请日：1989-02-09
IPC分类号： G11C11/00 , G11C11/404 , G11C14/00 , G11C11/40
CPC分类号： G11C11/005 , G11C11/404 , G11C14/00
摘要： A semiconductor memory device composed of a DRAM, an EEPROM, a mode switch means for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer means for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one capacitor, and one of the terminals of the capacitor is electrically isolated.
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6.发明授权Compact nonvolatile semiconductor memory device using stacked active and passive elements 失效紧凑型非易失性半导体存储器件，使用堆叠的有源和无源元件
公开(公告)号：US5172199A
公开(公告)日：1992-12-15
申请号：US711056
申请日：1991-06-06
IPC分类号： H01L27/112 , H01L21/8246 , H01L27/115 , H01L29/423
CPC分类号： H01L29/42324 , H01L27/115
摘要： A nonvolatile semiconductor memory device including a semiconductor substrate, a pair of impurity diffusion regions provided in the substrate, a gate region provided between the pair of impurity diffusion regions, a first gate electrode stacked on the gate region via a first dielectric film, and a second gate electrode stacked on the first gate electrode via a second dielectric film, the first gate electrode being electrically short-circuited to one of the impurity diffusion regions.
摘要翻译： 一种非易失性半导体存储器件，包括半导体衬底，设置在衬底中的一对杂质扩散区，设置在该对杂质扩散区之间的栅极区，经由第一绝缘膜堆叠在栅极区上的第一栅电极， 第二栅电极经由第二电介质膜堆叠在第一栅电极上，第一栅电极与一个杂质扩散区电短路。
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公开(公告)号：US5331181A
公开(公告)日：1994-07-19
申请号：US82511
申请日：1993-06-25
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/112 , H01L29/788 , H01L29/792 , H01L29/00 , H01L27/02 , H01L29/34 , H01L29/68
CPC分类号： H01L27/112
摘要： A non-volatile semiconductor memory providing a semiconductor substrate including source and drain diffusion regions and a gate electrode, and an insulating film which is at least provided on the semiconductor substrate just below the gate electrode and has a smaller dielectric breakdown strength on the source side than on the drain side, wherein the insulating film is comprised of a laminated film having a multilayer structure on the drain side and a single-layer film or multilayer film which is broken down at a smaller voltage on the source side than on the drain side, and a predetermined voltage is applied to break down the single-layer film or multilayer film on the source side, so that data can electrically be written only once.
摘要翻译： 提供包括源极和漏极扩散区域的半导体衬底和栅电极的非易失性半导体存储器以及至少设置在栅电极正下方的半导体衬底上并且在源极侧具有更小的介电击穿强度的绝缘膜 比在漏极侧，绝缘膜由在漏极侧具有多层结构的层叠膜和在源极侧的电压比在漏极侧分解的单层膜或多层膜 ，并且施加预定电压以分解源极侧的单层膜或多层膜，从而数据可以仅电一次写入。
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公开(公告)号：US5181188A
公开(公告)日：1993-01-19
申请号：US549293
申请日：1990-07-06
IPC分类号： G11C14/00
CPC分类号： G11C14/00
摘要： A semiconductor memory device having memory cells in which a DRAM section and an EEPROM section are combined, and a transistor for transferring data between the DRAM and EEPROM sections is disclosed. The DRAM section includes a MOS transistor, and a capacitor one electrode of which is connected to the source of the MOS transistor. The EEPROM section has a floating gate transistor. The transistor for transfer is connected between the source of the MOS transistor and the source/drain of the floating gate transistor. The control gate of the floating gate transistor is connected to the source of the MOS transistor. Methods of rewriting and recalling data in the semiconductor memory device are also disclosed. The methods can be performed without shortening the life of the EEPROM section.
摘要翻译： 公开了一种半导体存储器件，其具有其中组合有DRAM部分和EEPROM部分的存储单元，以及用于在DRAM和EEPROM部分之间传送数据的晶体管。 DRAM部分包括MOS晶体管，其一个电极的电容器连接到MOS晶体管的源极。 EEPROM部分具有浮栅晶体管。 用于传输的晶体管连接在MOS晶体管的源极和浮栅晶体管的源极/漏极之间。 浮栅晶体管的控制栅极连接到MOS晶体管的源极。 还公开了在半导体存储器件中重写和调用数据的方法。 可以在不缩短EEPROM部分的寿命的情况下执行这些方法。
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9.发明授权Semiconductor memory device having a volatile memory device and a non-volatile memory device 失效具有易失性存储器件和非易失性存储器件的半导体存储器件
公开(公告)号：US5140552A
公开(公告)日：1992-08-18
申请号：US687243
申请日：1991-04-18
IPC分类号： G11C11/00 , G11C11/404 , G11C14/00 , G11C16/04
CPC分类号： G11C11/005 , G11C11/404 , G11C14/00 , G11C16/04
摘要： A semiconductor memory device comprising a DRAM, an EEPROM, a mode switch circuit for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer circuit for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one capacitor, and one of the terminals of the capacitor is electrically isolated. The EEPROM consists of a floating gate and a control gate, and the mode switch circuit consists of a MOS transistor having a control gate integrally formed with the control gate of the EEPROM.
摘要翻译： 一种包括DRAM，EEPROM，用于选择DRAM模式和EEPROM模式的模式切换电路的半导体存储器件，以及用于将存储在DRAM中的数据传送到EEPROM的传输电路，反之亦然。 DRAM由一个晶体管和一个电容器组成，电容器的一个端子是电隔离的。 EEPROM由浮动栅极和控制栅极组成，模式开关电路由具有与EEPROM的控制栅极整体形成的控制栅极的MOS晶体管组成。
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公开(公告)号：US5043946A
公开(公告)日：1991-08-27
申请号：US490042
申请日：1990-03-07
IPC分类号： G11C11/00 , G11C11/404 , G11C14/00
CPC分类号： G11C11/005 , G11C11/404 , G11C14/00
摘要： A semiconductor memory device comprising a DRAM, an EEPROM, a mode switch for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer circuit for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one capacitor, and one of the terminals of the capacitor is electrically isolated.
摘要翻译： 一种包括DRAM，EEPROM，用于选择DRAM模式和EEPROM模式的模式的模式开关的半导体存储器件，以及用于将存储在DRAM中的数据传送到EEPROM的传输电路，反之亦然。 DRAM由一个晶体管和一个电容器组成，电容器的一个端子是电隔离的。
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