公开(公告)号：US5164806A

公开(公告)日：1992-11-17

申请号：US698690

申请日：1991-05-13

申请人： Masao Nagatomo ,  Hiroki Shimano ,  Tomonori Okudaira ,  Yoshinori Okumura

发明人： Masao Nagatomo ,  Hiroki Shimano ,  Tomonori Okudaira ,  Yoshinori Okumura

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/765

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/76216 ,  H01L21/765 ,  H01L29/6656 ,  Y10S257/90

摘要： An element isolating structure employed for isolating the elements of a semiconductor substrate has an impurity region having a concentration lower than that of a source/drain and a channel stop region, between the source/drain of an MOS transistor formed in an active region, and the channel stop region formed under an LOCOS film.A field shield isolating structure has a low concentrated impurity region between the source/drain of an MOS transistor formed in the active region and the substrate surface region covered by a field shield electrode layer. The low concentrated impurity region improves its junction breakdown voltage in the boundary region with the element isolating region.An improved LOCOS film is formed into an amorphous region on the surface of the substrate by an oblique rotating ion implanting method, and the amorphous region is formed by thermal oxidation. The method suppresses the emergence of a bird's beak.

摘要翻译： 用于隔离半导体衬底的元件的元件隔离结构具有在有源区中形成的MOS晶体管的源极/漏极之间具有低于源极/漏极和沟道截止区域的浓度的杂质区域和 在LOCOS膜下形成的通道停止区域。 场屏蔽隔离结构在有源区中形成的MOS晶体管的源极/漏极与由场屏蔽电极层覆盖的衬底表面区域之间具有低浓度杂质区域。 低浓度杂质区域改善了与元件隔离区域的边界区域的结击穿电压。 通过倾斜旋转离子注入方法将改进的LOCOS膜形成在衬底的表面上的非晶区域中，通过热氧化形成非晶区域。 该方法抑制鸟喙的出现。

公开(公告)号：US5428239A

公开(公告)日：1995-06-27

申请号：US71023

申请日：1993-06-03

申请人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

发明人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

IPC分类号： H01L27/10 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/823892 ,  H01L21/76221 ,  H01L21/823493 ,  H01L27/10805 ,  H01L27/0928 ,  H01L27/105

摘要： A DRAM is formed on a silicon substrate having a retrograde well and a diffusion-type well. The retrograde well has an impurity concentration profile which is set in steps by a plurality of ion-implantations. The diffusion-type well has an impurity concentration profile which changes monotonously by a thermal diffusion. A memory cell array is formed in the retrograde well region. A peripheral circuit is formed in the diffusion-type well region. The retrograde well enhances integration of devices included in the memory cell array. The diffusion-type well enhances the characteristic of insulating isolation between devices.

摘要翻译： 在具有逆行阱和扩散型阱的硅衬底上形成DRAM。 逆行井具有通过多个离子注入步骤设置的杂质浓度分布。 扩散型阱具有通过热扩散单调变化的杂质浓度分布。 在逆行井区域中形成记忆单元阵列。 在扩散型阱区域中形成外围电路。 逆行井增强了存储单元阵列中包含的器件的集成。 扩散型井增强了器件之间绝缘隔离的特性。

公开(公告)号：US5404042A

公开(公告)日：1995-04-04

申请号：US71925

申请日：1993-06-04

申请人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

发明人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L49/00 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/10805 ,  H01L27/0218 ,  H01L27/105

摘要： A semiconductor memory device in accordance with the present invention includes a plurality of n well regions and p well regions in a p type silicon substrate. One of the p well regions is connected to an external power supply. Peripheries of the p well region having a memory cell array formed therein are surrounded by an n well region having a potential held at a positive potential. The n well region held at the positive potential prevents electrons introduced into the substrate due to undershoot from entering into a p well region through the p well region connected to the external power supply.

摘要翻译： 根据本发明的半导体存储器件包括p型硅衬底中的多个n阱区和p阱区。 p个阱区中的一个连接到外部电源。 具有其中形成有存储单元阵列的p阱区的周边被具有保持在正电位的电位的n阱区围绕。 保持在正电位的n阱区防止由于下冲通过连接到外部电源的p阱区进入p阱区而引入到衬底中的电子。

公开(公告)号：US08148248B2

公开(公告)日：2012-04-03

申请号：US13053733

申请日：2011-03-22

申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

公开(公告)号：US20070077736A1

公开(公告)日：2007-04-05

申请号：US11537208

申请日：2006-09-29

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L21/04

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US06407419B1

公开(公告)日：2002-06-18

申请号：US09362669

申请日：1999-07-29

申请人： Tomonori Okudaira

发明人： Tomonori Okudaira

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11507 ,  H01L28/40

摘要： A semiconductor device preventing contact between a capacitor insulator and a plug material even when an upper surface of the plug is exposed by misregistration in lithography and manufacturing method thereof are obtained. The semiconductor device includes an interlayer insulating film, a conducting plug, a capacitor lower electrode and a capacitor dielectric, and an end portion of the upper surface of the conducting plug has a portion overlapping a vicinity of an outer periphery of the upper surface of the capacitor lower electrode when viewed two-dimensionally. In the vicinity of the end portion of the upper surface of the conducting plug, a chemically inactive member is formed.

摘要翻译： 即使当在光刻中通过不对准露出插头的上表面时，也可以防止电容器绝缘体和插塞材料之间的接触的半导体器件及其制造方法。 半导体器件包括层间绝缘膜，导电插塞，电容器下电极和电容器电介质，并且导电插塞的上表面的端部具有与所述导电插塞的上表面的外周附近重叠的部分 电容器下电极二维观察。 在导电塞的上表面的端部附近形成化学惰性部件。

公开(公告)号：US06078072A

公开(公告)日：2000-06-20

申请号：US73834

申请日：1998-05-06

申请人： Tomonori Okudaira ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L29/76 ,  H01L27/108 ,  H01L29/94 ,  H01L31/113

CPC分类号： H01L27/10852 ,  H01L28/60 ,  H01L28/55

摘要： A lower electrode layer 1 of a capacitor 10 is formed by sputtering performed at a temperature lower than 450.degree. C. in an atmosphere containing oxygen, and thereby the lower electrode layer 1 thus formed contains oxygen. Thereby, a method of manufacturing a semiconductor device having the capacitor can suppress current leak, and can prevent peeling of an electrode.

摘要翻译： 电容器10的下电极层1通过在低于450℃的温度下在含氧气氛中进行溅射而形成，由此形成的下电极层1含有氧。 因此，制造具有电容器的半导体器件的方法可以抑制电流泄漏，并且可以防止电极的剥离。

公开(公告)号：US06033732A

公开(公告)日：2000-03-07

申请号：US70009

申请日：1998-04-30

申请人： Akimasa Yuuki ,  Takaaki Kawahara ,  Tetsuro Makita ,  Mikio Yamamuka ,  Koichi Ono ,  Tomonori Okudaira

发明人： Akimasa Yuuki ,  Takaaki Kawahara ,  Tetsuro Makita ,  Mikio Yamamuka ,  Koichi Ono ,  Tomonori Okudaira

IPC分类号： C23C16/40 ,  C23C16/448 ,  C23C16/52 ,  C23C16/54 ,  C23C14/08

CPC分类号： C23C16/409 ,  C23C16/4481 ,  C23C16/52 ,  C23C16/54

摘要： A method of depositing a thin film on a substrate by chemical vapor deposition (CVD) including feeding a liquid CVD source material, including a solution in which at least one organometallic complex is dissolved in a solvent, at a constant flow rate to a vaporizer while keeping the CVD source material in a liquid state; vaporizing the liquid CVD source material by heating to form a CVD source material gas; and forming a thin film of a metal oxide on a substrate using the CVD material source gas in a reaction chamber, the thin film including at least titanium, including using TTIP and TiO(Dpm).sub.2 together as the organometallic complex.

摘要翻译： 一种通过化学气相沉积（CVD）在衬底上沉积薄膜的方法，包括将恒定流速的液态CVD源材料（包括其中至少一种有机金属配合物溶解在溶剂中）的溶液进料到蒸发器，同时 保持CVD源材料处于液态; 通过加热蒸发液体CVD源材料以形成CVD源材料气体; 以及使用所述CVD材料源气体在反应室中在基板上形成金属氧化物薄膜，所述薄膜至少包括钛，包括使用TTIP和TiO（Dpm）2作为有机金属络合物。

公开(公告)号：US5776254A

公开(公告)日：1998-07-07

申请号：US579495

申请日：1995-12-27

申请人： Akimasa Yuuki ,  Takaaki Kawahara ,  Tetsuro Makita ,  Mikio Yamamuka ,  Koichi Ono ,  Tomonori Okudaira

发明人： Akimasa Yuuki ,  Takaaki Kawahara ,  Tetsuro Makita ,  Mikio Yamamuka ,  Koichi Ono ,  Tomonori Okudaira

IPC分类号： C23C16/40 ,  C23C16/448 ,  C23C16/52 ,  C23C16/54 ,  C23C16/00

CPC分类号： C23C16/409 ,  C23C16/4481 ,  C23C16/52 ,  C23C16/54

摘要： A chemical vapor deposition (CVD) apparatus for depositing a thin film on a substrate by CVD has a material container for containing a liquid CVD source material, a material feeder for feeding the liquid CVD source material to a vaporizer for vaporizing the liquid CVD source material, and a reaction chamber for forming the thin film on the substrate using the CVD source material gas. Both the vaporizer and piping between the vaporizer and the reaction chamber are located in a thermostatic box surrounding the reaction chamber. Thus, the structure of the apparatus is simplified and also the heat efficiency of the apparatus is improved.

摘要翻译： 用于通过CVD在基板上沉积薄膜的化学气相沉积（CVD）装置具有用于容纳液体CVD源材料的材料容器，用于将液体CVD源材料供给到用于使液体CVD源材料蒸发的蒸发器的材料供料器 以及用于使用CVD源材料气体在基板上形成薄膜的反应室。 蒸发器和反应室之间的蒸发器和管道都位于围绕反应室的恒温箱中。 因此，简化了装置的结构，提高了装置的热效率。

公开(公告)号：US5218219A

公开(公告)日：1993-06-08

申请号：US678872

申请日：1991-04-04

申请人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10817

摘要： A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.

摘要翻译： 公开了一种动态随机存取存储器（DRAM），其即使在高集成器件中也能够有效地防止存储单元阵列101和外围电路102的边界区域中的步骤的形成。 该DRAM包括在存储单元阵列101的边界区域和P型硅衬底1的外围电路102的外围壁20a和20b的双周壁20，P型硅衬底1从P型硅衬底1垂直向上延伸。 形成在存储单元阵列上的器件的表面和外围电路102在存储单元阵列101和外围电路102上的形成装置中通过双周壁20的病毒基本平坦化，从而有效地防止了在步骤 存储单元阵列101和外围电路102的边界区域，即使在高集成器件中。