Comprehensive redundant load elimination for architectures supporting control and data speculation
    1.
    发明授权
    Comprehensive redundant load elimination for architectures supporting control and data speculation 失效
    支持控制和数据推测的架构的全面冗余负载消除

    公开(公告)号:US06202204B1

    公开(公告)日:2001-03-13

    申请号:US09038755

    申请日:1998-03-11

    IPC分类号: G06F945

    摘要: In one implementation of the invention, a computer implemented method used in compiling a program includes identifying a covering load, which may be one of a set of covering loads, and a redundant load. The covering load and the redundant load have a first and second load type, respectively. The first and the second load type each may be one of a group of load types including a regular load and at least one speculative-type load. In one implementation, the group of load types includes at least one check-type load. One implementation of the invention is in a machine readable medium.

    摘要翻译: 在本发明的一个实现中,用于编译程序的计算机实现方法包括识别可以是一组覆盖负载之一的覆盖负载和冗余负载。 覆盖负载和冗余负载分别具有第一和第二负载类型。 第一和第二负载类型各自可以是一组负载类型中的一种,包括常规负载和至少一个推测型负载。 在一个实现中,负载类型组包括至少一个检查类型的负载。 本发明的一个实施方案在机器可读介质中。

    INSTRUCTION AND LOGIC TO EFFICIENTLY MONITOR LOOP TRIP COUNT
    4.
    发明申请
    INSTRUCTION AND LOGIC TO EFFICIENTLY MONITOR LOOP TRIP COUNT 有权
    指令和逻辑到有效的监视器循环次数

    公开(公告)号:US20140208085A1

    公开(公告)日:2014-07-24

    申请号:US13996861

    申请日:2012-03-30

    IPC分类号: G06F9/32

    摘要: Logic and instruction to efficiently monitor loop trip count. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be applied or removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.

    摘要翻译: 有效监控回路行程数的逻辑和指令。 循环的循环行程计数信息可以存储在专用硬件缓冲器中。 可以基于存储的循环行程计数信息来计算循环的平均循环行程计数。 基于平均行程计数,循环优化可以从循环中应用或移除。 存储的循环行程计数信息可以包括标识循环的标识符,循环的总循环行程计数以及循环的退出计数。

    Power Gating Functional Units Of A Processor
    5.
    发明申请
    Power Gating Functional Units Of A Processor 有权
    处理器的电源门控功能单元

    公开(公告)号:US20130346781A1

    公开(公告)日:2013-12-26

    申请号:US13528548

    申请日:2012-06-20

    IPC分类号: G06F1/32 G06F9/30 G06F1/00

    摘要: In one embodiment, the present invention includes an apparatus having a core including functional units each to execute instructions of a target instruction set architecture (ISA) and a power controller to control a power mode of a first functional unit responsive to a power identification field of a power instruction of a power region of a code block to be executed on the core. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括一种具有核心的装置,其核心包括各自执行目标指令集架构(ISA)的指令的功能单元和功率控制器,以响应于功率识别领域来控制第一功能单元的功率模式 要在核心上执行的代码块的功率区域的功率指令。 描述和要求保护其他实施例。

    Context-sensitive slicing for dynamically parallelizing binary programs
    6.
    发明授权
    Context-sensitive slicing for dynamically parallelizing binary programs 有权
    用于动态并行化二进制程序的上下文相关切片

    公开(公告)号:US08443343B2

    公开(公告)日:2013-05-14

    申请号:US12607589

    申请日:2009-10-28

    IPC分类号: G06F9/45

    摘要: In one embodiment of the invention a method comprising (1) receiving an unstructured binary code region that is single-threaded; (2) determining a slice criterion for the region; (3) determining a call edge, a return edge, and a fallthrough pseudo-edge for the region based on analysis of the region at a binary level; and (4) determining a context-sensitive slice based on the call edge, the return edge, the fallthrough pseudo-edge, and the slice criterion. Embodiments of the invention may include a program analysis technique that can be used to provide context-sensitive slicing of binary programs for slicing hot regions identified at runtime, with few underlying assumptions about the program from which the binary is derived. Also, in an embodiment a slicing method may include determining a context-insensitive slice, when a time limit is met, by determining the context-insensitive slice while treating call edges as a normal control flow edges.

    摘要翻译: 在本发明的一个实施例中,一种方法包括(1)接收单线程的非结构化二进制码区域; (2)确定该区域的切片标准; (3)基于二进制级别的区域的分析确定该区域的通话边缘,返回边缘和下降伪边缘; 和(4)基于呼叫边缘,返回边缘,下降伪边缘和切片标准来确定上下文敏感切片。 本发明的实施例可以包括程序分析技术,其可以用于提供二进制程序的上下文敏感切片,用于对在运行时识别的热区域进行切片,而关于从其导出二进制的程序的几个基本假设。 此外,在一个实施例中,切片方法可以包括当满足时间限制时,通过在将呼叫边缘视为正常控制流边缘的同时确定上下文不敏感切片来确定上下文不敏感切片。

    Software flow tracking using multiple threads
    7.
    发明授权
    Software flow tracking using multiple threads 有权
    使用多线程的软件流跟踪

    公开(公告)号:US08321840B2

    公开(公告)日:2012-11-27

    申请号:US11965271

    申请日:2007-12-27

    IPC分类号: G06F9/44

    摘要: Methods, systems and machine readable media are disclosed for performing dynamic information flow tracking. One method includes executing operations of a program with a main thread, and tracking the main thread's execution of the operations of the program with a tracking thread. The method further includes updating, with the tracking thread, a taint value associated with the value of the main thread to reflect whether the value is tainted, and determining, with the tracking thread based upon the taint value, whether use of the value by the main thread violates a specific security policy.

    摘要翻译: 公开了用于执行动态信息流跟踪的方法,系统和机器可读介质。 一种方法包括执行具有主线程的程序的操作,并且使用跟踪线程跟踪主线程对程序的操作的执行。 该方法还包括利用跟踪线程来更新与主线程的值相关联的污点值,以反映该值是否被污染,并且基于该着色值确定跟踪线程是否使用该值 主线程违反了特定的安全策略。

    Efficient and consistent software transactional memory
    9.
    发明授权
    Efficient and consistent software transactional memory 有权
    高效一致的软件事务内存

    公开(公告)号:US08060482B2

    公开(公告)日:2011-11-15

    申请号:US11648012

    申请日:2006-12-28

    IPC分类号: G06F7/00 G06F17/00 G06F17/30

    摘要: A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.

    摘要翻译: 这里描述了用于在软件事务存储器(STM)系统中有效且一致的验证/冲突检测的方法和装置。 在加载之后插入版本检查障碍,以便在加载之前和之后比较加载值的版本。 此外,使用全局时间戳(GTS)来跟踪最近提交的事务。 每个事务与在事务开始时初始化为GTS值的本地时间戳(LTS)相关联。 作为事务提交,将GTS更新为新值,并将修改的位置的版本设置为新值。 待处理的交易将比较其在LTS阅读障碍中确定的版本。 如果版本大于其LTS,指示在挂起事务启动并初始化LTS之后另一个事务已经提交,则挂起的事务会验证其读取集合以保持有效且一致的事务执行。

    METHODS AND APPARATUS TO MANAGE PARTIAL-COMMIT CHECKPOINTS WITH FIXUP SUPPORT
    10.
    发明申请
    METHODS AND APPARATUS TO MANAGE PARTIAL-COMMIT CHECKPOINTS WITH FIXUP SUPPORT 有权
    使用固定支持管理部分提交检查的方法和设备

    公开(公告)号:US20110153999A1

    公开(公告)日:2011-06-23

    申请号:US12644151

    申请日:2009-12-22

    IPC分类号: G06F9/312

    摘要: Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.

    摘要翻译: 公开了用于管理部分提交检查点的示例性方法和装置。 所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令,从指令区域识别候选指令,以及生成处理器部分提交检查点以保存处理器的当前状态,所述检查点基于 与实时指令相关联的计算寄存器值,并包括链接候选指令的指令参考地址。