Precharge circuit having microprocessor-based firing angle control
circuitry
    6.
    发明授权
    Precharge circuit having microprocessor-based firing angle control circuitry 失效
    具有基于微处理器的触发角度控制电路的预充电电路

    公开(公告)号:US5483142A

    公开(公告)日:1996-01-09

    申请号:US124893

    申请日:1993-09-22

    摘要: A capacitor precharge circuit limits both peak DC link current and peak AC line current to any desired peak magnitude thereby providing for optimum precharge control and robust operation. The precharge circuit employs a microprocessor which implements a non-linear discontinuous current control scheme without the need for current sensors. The precharge circuit is well suited for use with an AC to DC converter having link inductor and a DC bus capacitor which requires precharging before full power is applied to the converter.

    摘要翻译: 电容器预充电电路将峰值DC链路电流和峰值AC线路电流限制到任何所需的峰值,从而提供最佳的预充电控制和鲁棒的操作。 预充电电路采用微处理器,其实现非线性不连续电流控制方案,而不需要电流传感器。 预充电电路非常适用于具有链路电感器和直流总线电容器的AC至DC转换器,该直流总线电容器在全功率被施加到转换器之前需要预充电。

    Bus bar having reduced parasitic inductances and equal current path
lengths
    7.
    发明授权
    Bus bar having reduced parasitic inductances and equal current path lengths 失效
    母线具有减小的寄生电感和相等的电流路径长度

    公开(公告)号:US5528073A

    公开(公告)日:1996-06-18

    申请号:US270340

    申请日:1994-07-05

    申请人: Thomas Gilmore

    发明人: Thomas Gilmore

    摘要: A bus bar having reduced parasitic inductance and equal current path legends. A bus bar of the present invention has a first plate connected to a collector of a first transistor, a collector of a second transistor, an emitter of a third transistor and an emitter of a fourth transistor; a second plate including a second plate input connected to a collector of the third transistor and a collector of the fourth transistor; a third plate including a third plate input connected to an emitter of the first transistor and an emitter of the second transistor; and a fourth plate which is connected to the first plate. The first plate, the second plate, and the third plate are disposed such that the lengths of the current paths from the fourth plate through the first transistor to the input of the third plate is equal to the length of the current path from the fourth plate through the second transistor to the input of the third plate. Similarly, the current path from the fourth plate through the third transistor to the input of the second plate is equal to the length of the current path from the fourth plate through the fourth transistor to the input of the second plate. A bus bar of the present invention has many advantages including reduced parasitic inductances, equal current path lengths, ease of construction, the ability to keep parallel transistor operating temperatures equal, and the inputs and output being located on the same side of the bus bar.

    摘要翻译: 具有减小的寄生电感和等电流路径图例的母线。 本发明的母线具有连接到第一晶体管的集电极,第二晶体管的集电极,第三晶体管的发射极和第四晶体管的发射极的第一板; 第二板,包括连接到第三晶体管的集电极的第二板输入端和第四晶体管的集电极; 第三板,包括连接到第一晶体管的发射极和第二晶体管的发射极的第三板输入端; 以及连接到第一板的第四板。 第一板,第二板和第三板被布置成使得从第四板通过第一晶体管到第三板的输入的电流路径的长度等于从第四板的电流路径的长度 通过第二晶体管到第三板的输入。 类似地,从第四板通过第三晶体管到第二板的输入的电流路径等于从第四板通过第四晶体管到第二板的输入的电流路径的长度。 本发明的母线具有许多优点,包括减小的寄生电感,等电流路径长度,易于构造,保持并联晶体管工作温度相等的能力,以及输入和输出位于母线的同一侧。

    Method and apparatus for two-piece box construction
    8.
    发明申请
    Method and apparatus for two-piece box construction 失效
    两件式箱体施工方法及装置

    公开(公告)号:US20050075231A1

    公开(公告)日:2005-04-07

    申请号:US10897999

    申请日:2004-07-23

    摘要: The present invention relates to a method and apparatus for a two-piece box construction which is a continuous, in-line process in which a pair of panels or blanks are fed simultaneously from one end of the apparatus and move along a substantially linear path through the apparatus where they are joined together so that upon exit from such apparatus the joined blanks can be fed directly, in line, into a conventional folder/gluer apparatus for final folding, gluing and other processing.

    摘要翻译: 本发明涉及一种用于两件式箱体结构的方法和装置,其是连续的在线方法,其中一对面板或坯料同时从装置的一端进给并沿着基本上线性的通路 它们连接在一起的装置,使得在从这种装置出来时,连接的坯件可以直接进给到一个常规的折叠/胶合器装置中,用于最终的折叠,胶合和其它处理。

    Bus bar having reduced parasitic inductances and equal current path
lengths
    9.
    发明授权
    Bus bar having reduced parasitic inductances and equal current path lengths 失效
    母线具有减小的寄生电感和相等的电流路径长度

    公开(公告)号:US5777377A

    公开(公告)日:1998-07-07

    申请号:US577317

    申请日:1995-12-22

    申请人: Thomas Gilmore

    发明人: Thomas Gilmore

    摘要: A bus bar having reduced parasitic inductance and equal current path lengths. A bus bar of the present invention has a first plate connected to a collector of a first transistor, a collector of a second transistor, an emitter of a third transistor and an emitter of a fourth transistor; a second plate including a second plate input connected to a collector of the third transistor and a collector of the fourth transistor; a third plate including a third plate input connected to an emitter of the first transistor and an emitter of the second transistor; and a fourth plate which is connected to the first plate. The first plate, the second plate, and the third plate are disposed and arranged such that the lengths of the current paths from the fourth plate through the first transistor to the input of the third plate is equal to the length of the current path from the fourth plate through the second transistor to the input of the third plate. Similarly, the current path from the fourth plate through the third transistor to the input of the second plate is equal to the length of the current path from the fourth plate through the fourth transistor to the input of the second plate. A bus bar of the present invention has many advantages including reduced parasitic inductances, equal current path lengths, ease of construction, the ability to keep parallel transistor operating temperatures equal, and the inputs and output being located on the same side of the bus bar. Additionally, a method of increasing converter efficiency is disclosed. The method comprises providing equal length current paths and planar structures that reduce parasitic inductances and maintain equal current sharing and temperature characteristics.

    摘要翻译: 具有降低的寄生电感和等电流路径长度的母线。 本发明的母线具有连接到第一晶体管的集电极,第二晶体管的集电极,第三晶体管的发射极和第四晶体管的发射极的第一板; 第二板,包括连接到第三晶体管的集电极的第二板输入端和第四晶体管的集电极; 第三板,包括连接到第一晶体管的发射极和第二晶体管的发射极的第三板输入端; 以及连接到第一板的第四板。 第一板,第二板和第三板被布置和布置成使得从第四板通过第一晶体管到第三板的输入的电流路径的长度等于从第三板的电流路径的长度 第四板通过第二晶体管到第三板的输入。 类似地,从第四板通过第三晶体管到第二板的输入的电流路径等于从第四板通过第四晶体管到第二板的输入的电流路径的长度。 本发明的母线具有许多优点,包括减小的寄生电感,等电流路径长度,易于构造,保持并联晶体管工作温度相等的能力,以及输入和输出位于母线的同一侧。 此外,公开了一种提高转换器效率的方法。 该方法包括提供相等长度的电流路径和减小寄生电感并保持相等的电流共享和温度特性的平面结构。

    Drill break-through sensor
    10.
    发明授权
    Drill break-through sensor 失效
    钻孔穿透传感器

    公开(公告)号:US4310269A

    公开(公告)日:1982-01-12

    申请号:US121994

    申请日:1980-02-19

    摘要: An improved power drill having means for sensing when the drill bit has penetrated through the workpiece and for then retracting the drill bit from the workpiece. An electrical signal responsive to the axial force between the drill and the drill bit is used to sense when the drill bit pierces the workpiece. A sudden decrease in the axial force triggers a mechanism for retracting the drill bit from the workpiece. Means are included to detect broken bits, missing bits and previously drilled holes.

    摘要翻译: 一种改进的电钻,具有用于感测钻头何时穿过工件并且然后从工件回缩钻头的装置。 使用响应于钻头和钻头之间的轴向力的电信号来感测钻头何时刺穿工件。 轴向力的突然下降触发了将钻头从工件回缩的机构。 包括检测碎点,丢失位和以前钻孔的手段。