公开(公告)号：US08044506B2

公开(公告)日：2011-10-25

申请号：US12181488

申请日：2008-07-29

申请人： Young Yun ,  Soo-Kyung Kim ,  Kwang-Seop Kim ,  Ki-Hyun Ko ,  Sung-Joo Park

发明人： Young Yun ,  Soo-Kyung Kim ,  Kwang-Seop Kim ,  Ki-Hyun Ko ,  Sung-Joo Park

IPC分类号： H01L23/34

CPC分类号： H01L23/467 ,  G11C5/04 ,  H01L2924/0002 ,  H05K1/0209 ,  H05K2201/0394 ,  H05K2201/09781 ,  H01L2924/00

摘要： The invention provides a thermal-emitting memory module, a thermal-emitting module socket, and a computer system comprising the thermal-emitting memory module and the thermal-emitting module socket. An embodiment of the thermal-emitting module includes: a module substrate having electrically-conductive traces; and a semiconductor device disposed on the module substrate and coupled to the electrically-conductive traces, the module substrate including a thermal-emitting portion disposed in proximity of the semiconductor device without directly contacting the semiconductor device.

摘要翻译： 本发明提供了一种发热存储器模块，热发射模块插座和包括热发射存储器模块和热发射模块插座的计算机系统。 热发射模块的一个实施例包括：具有导电迹线的模块衬底; 以及设置在所述模块基板上并耦合到所述导电迹线的半导体器件，所述模块基板包括设置在所述半导体器件附近的热发射部分而不直接接触所述半导体器件。

公开(公告)号：US08399301B2

公开(公告)日：2013-03-19

申请号：US13064081

申请日：2011-03-04

申请人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

发明人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

IPC分类号： H01L21/02

CPC分类号： H05K1/0246 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H01L2924/00

摘要： A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

摘要翻译： 集成电路模块的结构包括布线板，多个集成电路和至少一个终端电阻电路。 布线板在其至少一个表面上具有安装区域。 多个集成电路安装在布线板的安装区域中并沿第一方向彼此间隔开。 至少一个终端电阻电路被布置在至少两个相邻的集成电路之间，并且耦合到多个集成电路的最后一个的输出端。

公开(公告)号：US20110163418A1

公开(公告)日：2011-07-07

申请号：US13064082

申请日：2011-03-04

申请人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

发明人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

IPC分类号： H01L27/02

CPC分类号： H05K1/0246 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H01L2924/00

摘要： A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

公开(公告)号：US20110165736A1

公开(公告)日：2011-07-07

申请号：US13064081

申请日：2011-03-04

申请人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

发明人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

IPC分类号： H01L21/50

CPC分类号： H05K1/0246 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H01L2924/00

摘要： A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

摘要翻译： 集成电路模块的结构包括布线板，多个集成电路和至少一个终端电阻电路。 布线板在其至少一个表面上具有安装区域。 多个集成电路安装在布线板的安装区域中并沿第一方向彼此间隔开。 至少一个终端电阻电路被布置在至少两个相邻的集成电路之间，并且耦合到多个集成电路的最后一个的输出端。

公开(公告)号：US20080179649A1

公开(公告)日：2008-07-31

申请号：US12010138

申请日：2008-01-22

申请人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

发明人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

IPC分类号： H01L29/94 ,  H01L21/00

CPC分类号： H05K1/0246 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H01L2924/00

摘要： A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

摘要翻译： 集成电路模块的结构包括布线板，多个集成电路和至少一个终端电阻电路。 布线板在其至少一个表面上具有安装区域。 多个集成电路安装在布线板的安装区域中并沿第一方向彼此间隔开。 至少一个终端电阻电路被布置在至少两个相邻的集成电路之间，并且耦合到多个集成电路的最后一个的输出端。

公开(公告)号：US07919841B2

公开(公告)日：2011-04-05

申请号：US12010138

申请日：2008-01-22

申请人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

发明人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

IPC分类号： H01L23/02

CPC分类号： H05K1/0246 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H01L2924/00

摘要： A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

公开(公告)号：US08144481B2

公开(公告)日：2012-03-27

申请号：US12632853

申请日：2009-12-08

申请人： Sung-Joo Park ,  Ki-Hyun Ko ,  Myung-Hee Sung

发明人： Sung-Joo Park ,  Ki-Hyun Ko ,  Myung-Hee Sung

IPC分类号： H01R9/00

CPC分类号： H05K1/0246 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10159

摘要： A memory system includes; a main board having memory bus with a wiring line communicating a signal from a memory controller mounted on the main board, first and second module sockets mounted on the main board and connecting the wiring line to first and second memory modules respectively inserted into the first and second module sockets, where the first memory module includes a first electrode connected to the wiring line and the second memory module includes a second electrode connected to the wiring line, and first and second stub resistors disposed on the main board and arranged as primary dual-branching stub resistors forming a T-branch connection structure between the first and second electrodes and a branching node connected to the wiring line.

摘要翻译： 存储系统包括： 具有存储器总线的主板，具有用于传送来自安装在主板上的存储器控​​制器的信号的布线的布线;安装在主板上的第一和第二模块插槽，并将布线连接到分别插入第一和第二存储器模块的第一和第二存储器模块; 第二模块插座，其中第一存储器模块包括连接到布线的第一电极，并且第二存储器模块包括连接到布线的第二电极，以及设置在主板上并被布置为主要双绞线的第一和第二短截线电阻器， 在第一和第二电极之间形成T分支连接结构的分支短截线电阻器和连接到布线的分支节点。

公开(公告)号：US06836138B1

公开(公告)日：2004-12-28

申请号：US10795507

申请日：2004-03-09

申请人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee

发明人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee

IPC分类号： G01R3126

CPC分类号： H05K1/0268 ,  G01R1/0483 ,  G01R31/31905 ,  G11C29/48 ,  G11C2029/5602 ,  H01L2224/48091 ,  H01L2224/859 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/111 ,  H05K2201/10734 ,  H01L2924/00014

摘要： A ball grid array (BGA) package test module includes BGA packages, a module board, and test architecture for use in testing the BGA packages while they are mounted to the module board. The test architecture of the BGA package test module includes package test signal lines connected to solder balls of the BGA packages as extending along a bottom surface of the BGA packages, board test signal lines extending along the module board, and electrical junctions that interconnect the package and board test signal lines. Signals from the BGA packages can be picked up by the probe of a testing apparatus via the board test signal lines. The present invention is advantageous in that it minimizes the effect of stubbing by the test signal lines when the memory module is operating.

摘要翻译： 球栅阵列（BGA）封装测试模块包括BGA封装，模块板和测试架构，用于在安装到模块板时测试BGA封装。 BGA封装测试模块的测试架构包括连接到BGA封装的焊球的封装测试信号线，沿BGA封装的底表面延伸，沿着模块板延伸的板测试信号线，以及将封装相互连接的电连接 和板测试信号线。 来自BGA封装的信号可以由测试装置的探头通过板测试信号线拾取。 本发明的优点在于，当存储器模块运行时，其最小化由测试信号线引起的短截线的影响。

公开(公告)号：US08036051B2

公开(公告)日：2011-10-11

申请号：US12355421

申请日：2009-01-16

申请人： Sung-Joo Park ,  Jae-Jun Lee

发明人： Sung-Joo Park ,  Jae-Jun Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/1048 ,  G11C7/12 ,  G11C29/02 ,  G11C29/025

摘要： A semiconductor memory device and a semiconductor memory system. The semiconductor memory device includes channels configured to transmit signals from a transmitter to a receiver, and a crosstalk compensator. The crosstalk compensator may be connected between the channels to compensate for crosstalk. The crosstalk compensator may comprise a capacitor connected in parallel between the channels, and a switching unit connected between the capacitor and one of the channels. The switching unit may control connections or disconnections between the capacitor and the channel. Therefore, the semiconductor memory device and the semiconductor memory system compensate for crosstalk occurring between transmitted signals that are out of phase with each other.

摘要翻译： 半导体存储器件和半导体存储器系统。 半导体存储器件包括被配置为将信号从发送器发送到接收器的通道和串扰补偿器。 串扰补偿器可以连接在通道之间以补偿串扰。 串扰补偿器可以包括在通道之间并联连接的电容器，以及连接在电容器和其中一个通道之间的开关单元。 开关单元可以控制电容器和通道之间的连接或断开。 因此，半导体存储器件和半导体存储器系统补偿在彼此不同相位的发射信号之间发生的串扰。

公开(公告)号：US07652949B2

公开(公告)日：2010-01-26

申请号：US11633353

申请日：2006-12-04

申请人： Chil-Nam Yoon ,  Young-Man Ahn ,  Young-Jun Park ,  Sung-Joo Park

发明人： Chil-Nam Yoon ,  Young-Man Ahn ,  Young-Jun Park ,  Sung-Joo Park

IPC分类号： G11C8/18

CPC分类号： G11C8/18 ,  G11C5/04 ,  G11C5/063

摘要： A memory module includes a first memory group including a plurality of memory devices, a second memory group including a less number of memory devices with respect to the memory devices in the first memory group, a register configured to provide a command/address signal to the first memory group and a delayed command/address signal to the second memory group, a first signal line configured to transfer the command/address signal to the first memory group, and a second signal line configured to transfer the delayed command/address signal to the second memory group.

摘要翻译： 存储器模块包括包括多个存储器件的第一存储器组，包括相对于第一存储器组中的存储器件的较少数量的存储器件的第二存储器组，配置成向第一存储器组件提供命令/地址信号的寄存器 第一存储器组和延迟的命令/地址信号到第二存储器组，第一信号线，被配置为将命令/地址信号传送到第一存储器组;以及第二信号线，被配置为将延迟的命令/地址信号传送到 第二内存组。