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    Memory system with improved signal integrity
    1.
    发明申请
    Memory system with improved signal integrity 审中-公开
    具有改善信号完整性的存储系统

    公开(公告)号：US20050002241A1

    公开(公告)日：2005-01-06

    申请号：US10837610

    申请日：2004-05-04

    申请人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Chil-Nam Yoon

    发明人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Chil-Nam Yoon

    IPC分类号： G06F12/00 ,  G06F13/40 ,  G11C5/00 ,  G11C5/06

    CPC分类号： G06F13/4086

    摘要： A memory system includes a memory controller, a memory bus connected to the memory controller, and a plurality of memory modules connected along the memory bus, where each of the memory modules includes a plurality of memory devices. The system also includes a dummy stub or a dummy module connected to the memory bus between the memory controller and the memory module closest to the memory controller among the plurality of memory modules. The dummy stub or dummy module improves a signal integrity of at least the memory module closest to the memory controller.

    摘要翻译： 存储器系统包括存储器控制器，连接到存储器控制器的存储器总线以及沿着存储器总线连接的多个存储器模块，其中每个存储器模块包括多个存储器件。 该系统还包括连接到存储器总线之间的存储器控​​制器和位于多个存储器模块中最靠近存储器控制器的存储器模块之间的虚拟存根或虚拟模块。 虚拟短线或虚拟模块改善了至少与存储器控制器最接近的存储器模块的信号完整性。

    Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same
    2.
    发明授权
    Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same 失效
    具有用于促进球栅阵列封装测试的测试架构的模块，以及使用其的测试方法

    公开(公告)号：US06836138B1

    公开(公告)日：2004-12-28

    申请号：US10795507

    申请日：2004-03-09

    申请人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee

    发明人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee

    IPC分类号： G01R3126

    CPC分类号： H05K1/0268 ,  G01R1/0483 ,  G01R31/31905 ,  G11C29/48 ,  G11C2029/5602 ,  H01L2224/48091 ,  H01L2224/859 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/111 ,  H05K2201/10734 ,  H01L2924/00014

    摘要： A ball grid array (BGA) package test module includes BGA packages, a module board, and test architecture for use in testing the BGA packages while they are mounted to the module board. The test architecture of the BGA package test module includes package test signal lines connected to solder balls of the BGA packages as extending along a bottom surface of the BGA packages, board test signal lines extending along the module board, and electrical junctions that interconnect the package and board test signal lines. Signals from the BGA packages can be picked up by the probe of a testing apparatus via the board test signal lines. The present invention is advantageous in that it minimizes the effect of stubbing by the test signal lines when the memory module is operating.

    摘要翻译： 球栅阵列（BGA）封装测试模块包括BGA封装，模块板和测试架构，用于在安装到模块板时测试BGA封装。 BGA封装测试模块的测试架构包括连接到BGA封装的焊球的封装测试信号线，沿BGA封装的底表面延伸，沿着模块板延伸的板测试信号线，以及将封装相互连接的电连接 和板测试信号线。 来自BGA封装的信号可以由测试装置的探头通过板测试信号线拾取。 本发明的优点在于，当存储器模块运行时，其最小化由测试信号线引起的短截线的影响。

    Memory module and a method of arranging a signal line of the same
    5.
    发明授权
    Memory module and a method of arranging a signal line of the same 失效
    存储器模块及其配置信号线的方法

    公开(公告)号：US07106613B2

    公开(公告)日：2006-09-12

    申请号：US11064671

    申请日：2005-02-24

    申请人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

    发明人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

    摘要： The present invention discloses a memory module and a method of arranging a signal line of the same. The method of arranging a signal line of a memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line.

    摘要翻译： 本发明公开了一种存储模块及其配置信号线的方法。 布置存储器模块的信号线的方法包括：将多个存储器分类为包括奇数个存储器的第一组和包括偶数个存储器的第二组; 布置与多个存储器相对应的第一分支点，并通过第一信号线分别将第一分支点连接到多个存储器; 布置位于第二组中间的第二分支点，以分别连接第二组彼此相邻的第一分支点与第二分支点相邻的第一分支点与第二分支点之间通过第二信号线 ; 布置位于第二组中间的第三分支点，接收外部信号，并通过第三信号线连接第二组的第三分支点和第二分支点; 并且通过第四信号线连接第二组的第二分支点和第一组的第一分支点。

    Memory module with memory devices of different capacity
    6.
    发明申请
    Memory module with memory devices of different capacity 审中-公开
    内存模块具有不同容量的内存设备

    公开(公告)号：US20060059298A1

    公开(公告)日：2006-03-16

    申请号：US11102181

    申请日：2005-04-08

    申请人： Jeong-Hyeon Cho ,  Jung-Joon Lee ,  You-Keun Han ,  Byung-Se So

    发明人： Jeong-Hyeon Cho ,  Jung-Joon Lee ,  You-Keun Han ,  Byung-Se So

    IPC分类号： G06F12/00

    CPC分类号： G11C5/04

    摘要： A memory module includes a first set of at least one first type of memory device and a second set of at least one second type of memory device having a higher capacity than the first type. In addition, an additional capacity portion of the first and second sets stores information for an additional function of the memory module, and a remaining capacity portion of the first and second sets forms a rank of the memory module. The memory module avoids an asymmetric topology of signal lines and yet provides additional memory capacity.

    摘要翻译： 存储器模块包括具有比第一类型更高的容量的至少一种第一类型的存储器件的第一组和至少一种第二类型的存储器件的第二组。 此外，第一组和第二组的附加容量部分存储用于存储器模块的附加功能的信息，并且第一组和第二组的剩余容量部分形成存储器模块的等级。 存储器模块避免信号线的不对称拓扑，并提供额外的存储容量。

    Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted
    7.
    发明授权
    Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted 失效
    具有镜像结构和双列直插存储器模块的堆叠板上芯片封装，其上安装有堆叠板上芯片封装

    公开(公告)号：US07276786B2

    公开(公告)日：2007-10-02

    申请号：US11177736

    申请日：2005-07-08

    申请人： Jeong-Hyeon Cho ,  Jung-Joon Lee ,  Do-Hyung Kim ,  Byung-Se So

    发明人： Jeong-Hyeon Cho ,  Jung-Joon Lee ,  Do-Hyung Kim ,  Byung-Se So

    IPC分类号： H01L23/42 ,  H01L23/58 ,  H01L29/40

    CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L25/16 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/00014

    摘要： Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.

    摘要翻译： 本发明的实施例包括具有镜像结构的堆叠板上芯片（BOC）封装和其上安装有堆叠的BOC封装的双列直插存储器模块（DIMM）。 第一半导体芯片的底面朝向第二半导体芯片的底面。 插入器将分别包括第一和第二半导体芯片的第一和第二封装彼此电连接。 通过在印刷电路板的上下基板上将BOC封装彼此电连接来获得DIMM。 由于堆叠的BOC封装的高度大于常规堆叠BOC封装的高度，所以DIMM具有最小的短截线长度和最佳拓扑。 因此，通过减少信号线上的负载，DIMM可以具有出色的保真度的信号，并且DIMM 300内的组件的安装或接线需要较少的努力。

    Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted
    8.
    发明申请
    Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted 失效
    堆叠的片上芯片封装，具有镜像结构和双列直插存储器模块，其上安装有堆叠的片上芯片封装

    公开(公告)号：US20060055017A1

    公开(公告)日：2006-03-16

    申请号：US11177736

    申请日：2005-07-08

    申请人： Jeong-Hyeon Cho ,  Jung-Joon Lee ,  Do-Hyung Kim ,  Byung-Se So

    发明人： Jeong-Hyeon Cho ,  Jung-Joon Lee ,  Do-Hyung Kim ,  Byung-Se So

    IPC分类号： H01L23/02

    CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L25/16 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/00014

    摘要： Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.

    摘要翻译： 本发明的实施例包括具有镜像结构的堆叠板上芯片（BOC）封装和其上安装有堆叠的BOC封装的双列直插存储器模块（DIMM）。 第一半导体芯片的底面朝向第二半导体芯片的底面。 插入器将分别包括第一和第二半导体芯片的第一和第二封装彼此电连接。 通过在印刷电路板的上下基板上将BOC封装彼此电连接来获得DIMM。 由于堆叠的BOC封装的高度大于常规堆叠BOC封装的高度，所以DIMM具有最小的短截线长度和最佳拓扑。 因此，通过减少信号线上的负载，DIMM可以具有出色的保真度的信号，并且DIMM 300内的组件的安装或接线需要较少的努力。

    Memory module and a method of arranging a signal line of the same
    9.
    发明申请
    Memory module and a method of arranging a signal line of the same 失效
    存储器模块及其配置信号线的方法

    公开(公告)号：US20050185439A1

    公开(公告)日：2005-08-25

    申请号：US11064671

    申请日：2005-02-24

    申请人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

    发明人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

    IPC分类号： G06F12/00 ,  G11C5/06 ,  G11C11/401 ,  H05K1/18

    CPC分类号： G11C5/063 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

    摘要： The present invention discloses a memory module and a method of arranging a signal line of the same. The method of arranging a signal line of a memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line.

    摘要翻译： 本发明公开了一种存储模块及其配置信号线的方法。 布置存储器模块的信号线的方法包括：将多个存储器分类为包括奇数个存储器的第一组和包括偶数个存储器的第二组; 布置与多个存储器相对应的第一分支点，并通过第一信号线分别将第一分支点连接到多个存储器; 布置位于第二组中间的第二分支点，以分别连接第二组彼此相邻的第一分支点与第二分支点相邻的第一分支点与第二分支点之间通过第二信号线 ; 布置位于第二组中间的第三分支点，接收外部信号，并通过第三信号线连接第二组的第三分支点和第二分支点; 并且通过第四信号线连接第二组的第二分支点和第一组的第一分支点。

    Multi-chip package for reducing parasitic load of pin
    10.
    发明授权
    Multi-chip package for reducing parasitic load of pin 有权
    用于减少引脚寄生负载的多芯片封装

    公开(公告)号：US07566958B2

    公开(公告)日：2009-07-28

    申请号：US11589192

    申请日：2006-10-30

    申请人： Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

    发明人： Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

    IPC分类号： H01L23/02

    CPC分类号： H01L24/49 ,  G11C5/00 ,  G11C5/06 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

    摘要翻译： 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。 此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。