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    Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same
    1.
    发明授权
    Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same 失效
    具有用于促进球栅阵列封装测试的测试架构的模块，以及使用其的测试方法

    公开(公告)号：US06836138B1

    公开(公告)日：2004-12-28

    申请号：US10795507

    申请日：2004-03-09

    申请人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee

    发明人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee

    IPC分类号： G01R3126

    CPC分类号： H05K1/0268 ,  G01R1/0483 ,  G01R31/31905 ,  G11C29/48 ,  G11C2029/5602 ,  H01L2224/48091 ,  H01L2224/859 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/111 ,  H05K2201/10734 ,  H01L2924/00014

    摘要： A ball grid array (BGA) package test module includes BGA packages, a module board, and test architecture for use in testing the BGA packages while they are mounted to the module board. The test architecture of the BGA package test module includes package test signal lines connected to solder balls of the BGA packages as extending along a bottom surface of the BGA packages, board test signal lines extending along the module board, and electrical junctions that interconnect the package and board test signal lines. Signals from the BGA packages can be picked up by the probe of a testing apparatus via the board test signal lines. The present invention is advantageous in that it minimizes the effect of stubbing by the test signal lines when the memory module is operating.

    摘要翻译： 球栅阵列（BGA）封装测试模块包括BGA封装，模块板和测试架构，用于在安装到模块板时测试BGA封装。 BGA封装测试模块的测试架构包括连接到BGA封装的焊球的封装测试信号线，沿BGA封装的底表面延伸，沿着模块板延伸的板测试信号线，以及将封装相互连接的电连接 和板测试信号线。 来自BGA封装的信号可以由测试装置的探头通过板测试信号线拾取。 本发明的优点在于，当存储器模块运行时，其最小化由测试信号线引起的短截线的影响。

    Memory system with improved signal integrity
    2.
    发明申请
    Memory system with improved signal integrity 审中-公开
    具有改善信号完整性的存储系统

    公开(公告)号：US20050002241A1

    公开(公告)日：2005-01-06

    申请号：US10837610

    申请日：2004-05-04

    申请人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Chil-Nam Yoon

    发明人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Chil-Nam Yoon

    IPC分类号： G06F12/00 ,  G06F13/40 ,  G11C5/00 ,  G11C5/06

    CPC分类号： G06F13/4086

    摘要： A memory system includes a memory controller, a memory bus connected to the memory controller, and a plurality of memory modules connected along the memory bus, where each of the memory modules includes a plurality of memory devices. The system also includes a dummy stub or a dummy module connected to the memory bus between the memory controller and the memory module closest to the memory controller among the plurality of memory modules. The dummy stub or dummy module improves a signal integrity of at least the memory module closest to the memory controller.

    摘要翻译： 存储器系统包括存储器控制器，连接到存储器控制器的存储器总线以及沿着存储器总线连接的多个存储器模块，其中每个存储器模块包括多个存储器件。 该系统还包括连接到存储器总线之间的存储器控​​制器和位于多个存储器模块中最靠近存储器控制器的存储器模块之间的虚拟存根或虚拟模块。 虚拟短线或虚拟模块改善了至少与存储器控制器最接近的存储器模块的信号完整性。

    Data receiver, semiconductor device and memory device including the same
    3.
    发明授权
    Data receiver, semiconductor device and memory device including the same 有权
    数据接收器，半导体器件和包括其的存储器件

    公开(公告)号：US08559241B2

    公开(公告)日：2013-10-15

    申请号：US13110161

    申请日：2011-05-18

    申请人： Sung-Joo Park ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    发明人： Sung-Joo Park ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C8/06

    摘要： A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

    摘要翻译： 数据接收机包括第一缓冲电路和第二缓冲电路。 第一缓冲电路基于多个控制信号改变数据路径的电阻和参考电压路径的电阻，并且调整输入数据信号的电压电平和参考电压的电平以产生内部数据信号 以及基于数据路径的变化的电阻和参考电压路径的变化的电阻的内部参考电压。 第二缓冲电路将内部数据信号与内部参考电压进行比较以产生数据信号。

    Memory module, memory module socket and mainboard using same
    5.
    发明授权
    Memory module, memory module socket and mainboard using same 有权
    内存模块，内存模块插座和主板使用相同

    公开(公告)号：US07540743B2

    公开(公告)日：2009-06-02

    申请号：US11836286

    申请日：2007-08-09

    申请人： Sung-Joo Park ,  Kyoung-Sun Kim ,  Jung-Joon Lee ,  Jea-Eun Lee

    发明人： Sung-Joo Park ,  Kyoung-Sun Kim ,  Jung-Joon Lee ,  Jea-Eun Lee

    IPC分类号： H01R12/00

    CPC分类号： H01R12/83 ,  H01R13/62988 ,  H01R13/631 ,  H05K1/0295 ,  H05K1/117 ,  H05K2201/09954 ,  H05K2201/10159

    摘要： A memory module socket disposed on a principal surface of a mainboard, and adapted to mechanically receive and electrically connect a memory module with a mainboard, the memory module socket including a first unit socket having a plurality of first socket pins adapted to electrically connect a first connector disposed on an edge of the memory module, and a second unit socket having a plurality of second socket pins adapted to electrically connect to a second connector disposed on the memory module orthogonal to the first connector, wherein the memory module as installed in the memory module socket is parallel to the principal surface of the mainboard.

    摘要翻译： 存储模块插座，设置在主板的主表面上，并且适于机械地接收和电连接存储器模块与主板，所述存储器模块插座包括第一单元插座，所述第一单元插座具有多个第一插座引脚，所述第一插座引脚适于电连接第一 连接器，其设置在存储器模块的边缘上，以及第二单元插座，其具有多个第二插座引脚，其适于电连接到设置在与第一连接器正交的存储器模块上的第二连接器，其中存储器模块安装在存储器 模块插座平行于主板的主表面。

    Mounting structures for integrated circuit modules
    7.
    发明授权
    Mounting structures for integrated circuit modules 有权
    集成电路模块的安装结构

    公开(公告)号：US08399301B2

    公开(公告)日：2013-03-19

    申请号：US13064081

    申请日：2011-03-04

    申请人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

    发明人： Sung-Joo Park ,  Ki-Hyun Ko ,  Young Yun ,  Soo-Kyung Kim

    IPC分类号： H01L21/02

    CPC分类号： H05K1/0246 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H01L2924/00

    摘要： A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

    摘要翻译： 集成电路模块的结构包括布线板，多个集成电路和至少一个终端电阻电路。 布线板在其至少一个表面上具有安装区域。 多个集成电路安装在布线板的安装区域中并沿第一方向彼此间隔开。 至少一个终端电阻电路被布置在至少两个相邻的集成电路之间，并且耦合到多个集成电路的最后一个的输出端。

    Semiconductor memory device and semiconductor memory system for compensating crosstalk
    8.
    发明授权
    Semiconductor memory device and semiconductor memory system for compensating crosstalk 失效
    用于补偿串扰的半导体存储器件和半导体存储器系统

    公开(公告)号：US08036051B2

    公开(公告)日：2011-10-11

    申请号：US12355421

    申请日：2009-01-16

    申请人： Sung-Joo Park ,  Jae-Jun Lee

    发明人： Sung-Joo Park ,  Jae-Jun Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C7/02 ,  G11C7/1048 ,  G11C7/12 ,  G11C29/02 ,  G11C29/025

    摘要： A semiconductor memory device and a semiconductor memory system. The semiconductor memory device includes channels configured to transmit signals from a transmitter to a receiver, and a crosstalk compensator. The crosstalk compensator may be connected between the channels to compensate for crosstalk. The crosstalk compensator may comprise a capacitor connected in parallel between the channels, and a switching unit connected between the capacitor and one of the channels. The switching unit may control connections or disconnections between the capacitor and the channel. Therefore, the semiconductor memory device and the semiconductor memory system compensate for crosstalk occurring between transmitted signals that are out of phase with each other.

    摘要翻译： 半导体存储器件和半导体存储器系统。 半导体存储器件包括被配置为将信号从发送器发送到接收器的通道和串扰补偿器。 串扰补偿器可以连接在通道之间以补偿串扰。 串扰补偿器可以包括在通道之间并联连接的电容器，以及连接在电容器和其中一个通道之间的开关单元。 开关单元可以控制电容器和通道之间的连接或断开。 因此，半导体存储器件和半导体存储器系统补偿在彼此不同相位的发射信号之间发生的串扰。

    Memory module and register with minimized routing path
    9.
    发明授权
    Memory module and register with minimized routing path 失效
    内存模块和注册最小化路由路径

    公开(公告)号：US07652949B2

    公开(公告)日：2010-01-26

    申请号：US11633353

    申请日：2006-12-04

    申请人： Chil-Nam Yoon ,  Young-Man Ahn ,  Young-Jun Park ,  Sung-Joo Park

    发明人： Chil-Nam Yoon ,  Young-Man Ahn ,  Young-Jun Park ,  Sung-Joo Park

    IPC分类号： G11C8/18

    CPC分类号： G11C8/18 ,  G11C5/04 ,  G11C5/063

    摘要： A memory module includes a first memory group including a plurality of memory devices, a second memory group including a less number of memory devices with respect to the memory devices in the first memory group, a register configured to provide a command/address signal to the first memory group and a delayed command/address signal to the second memory group, a first signal line configured to transfer the command/address signal to the first memory group, and a second signal line configured to transfer the delayed command/address signal to the second memory group.

    摘要翻译： 存储器模块包括包括多个存储器件的第一存储器组，包括相对于第一存储器组中的存储器件的较少数量的存储器件的第二存储器组，配置成向第一存储器组件提供命令/地址信号的寄存器 第一存储器组和延迟的命令/地址信号到第二存储器组，第一信号线，被配置为将命令/地址信号传送到第一存储器组;以及第二信号线，被配置为将延迟的命令/地址信号传送到 第二内存组。

    Apparatus and method for creating 3-dimensional image
    10.
    发明申请
    Apparatus and method for creating 3-dimensional image 失效
    用于创建三维图像的装置和方法

    公开(公告)号：US20070120843A1

    公开(公告)日：2007-05-31

    申请号：US10574705

    申请日：2004-10-06

    申请人： Sung-Joo Park ,  Se-Yern Oh

    发明人： Sung-Joo Park ,  Se-Yern Oh

    IPC分类号： G06T15/00

    CPC分类号： G03B35/00 ,  G06T1/0007

    摘要： The present invention relates to a apparatus and method for generating 3-dimensional image, which comprises a image photographing part composed of a camera part, a turn table part, a photographing angle adjustment part, a X-axis adjustment part, and a Y-axis adjustment part; a image photographing control part that creates movement control signals, transmits to said image photographing part, and receives plural digital images photographed by said camera part; a 3-dimensional image generating part that creates 3 dimensional images by using said plural digital images; and a storage part that stores said plural digital images and said 3-dimensional images. The present invention thus provides 3-dimensional images to consumers to see a certain product with its actual view by rotating at a wanted angle.

    摘要翻译： 本发明涉及一种用于生成三维图像的装置和方法，该装置和方法包括由相机部分，转台部分，拍摄角度调节部分，X轴调节部分和Y轴调节部分组成的图像拍摄部分， 轴调整部; 创建移动控制信号的图像拍摄控制部分，发送到所述图像拍摄部分，并且接收由所述相机部分拍摄的多个数字图像; 通过使用所述多个数字图像来生成3维图像的3维图像生成部; 以及存储所述多个数字图像和所述3维图像的存储部。 因此，本发明为消费者提供了三维图像，以通过以所需角度旋转来观察具有实际视角的某种产品。