公开(公告)号：US20160099170A1

公开(公告)日：2016-04-07

申请号：US14943532

申请日：2015-11-17

Applicant: Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

Inventor： Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

IPC: H01L21/768 ,  H01L27/24 ,  H01L21/3213 ,  H01L27/115 ,  H01L21/311

CPC classification number: H01L23/498 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/441 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/49844 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

Abstract translation: 提供了形成由此制造的电极堆叠和三维半导体器件的方法。 该装置可以包括依次层叠在基板上以构成电极结构的电极。 每个电极可以包括从位于其上的一个电极的侧壁水平和向外突出的连接部分和具有与位于其上的电极之一的侧壁共面的对准部分。 这里，彼此垂直相邻设置的电极中的至少两个可以以这样的方式设置，使得其对准的部分具有基本上对准以彼此共面的侧壁。

公开(公告)号：US20120178234A1

公开(公告)日：2012-07-12

申请号：US13324035

申请日：2011-12-13

Applicant: Young-Ho LEE ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

Inventor： Young-Ho LEE ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

IPC: H01L21/8239

CPC classification number: H01L27/0629 ,  H01L27/11531 ,  H01L28/20

Abstract: In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

Abstract translation: 在集成电路器件及其制造方法中，电阻器图案位于衬底的器件隔离层上。 电阻器图案包括位于器件隔离层的凹部中的电阻体，以及与电阻体接触并连接在凹部的周围的器件隔离层上的连接器。 连接器具有在上部具有低于电阻体的电阻的金属硅化物图案。 栅极图案位于衬底的有源区上，并且在上部包括金属硅化物图案。 提供电阻器互连以与电阻器图案的连接器接触。 连接器和电阻器互连之间的接触电阻降低。

公开(公告)号：US20080224212A1

公开(公告)日：2008-09-18

申请号：US11965559

申请日：2007-12-27

Applicant: Young-Ho LEE ,  Dong-Sun Sheen ,  Seok-Pyo Song

Inventor： Young-Ho LEE ,  Dong-Sun Sheen ,  Seok-Pyo Song

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is provided. A first insulation layer and a second insulation layer are formed over the substrate having a gate. A spacer etching process is performed to form an etched first insulation layer and an etched second insulation layer. The etched first insulation layer partially protrudes from the substrate and contacts sidewalls of the gate. The etched second insulation layer is removed through a selective epitaxial growth (SEG) process that forms an epitaxial layer over the exposed substrate. One of facets of the epitaxial layer is formed on the protruding portion of the etched first insulation layer. A third insulation layer is formed on sidewalls of the etched first insulation layer and the one of the facets of the epitaxial layer is covered by the third insulation layer.

Abstract translation: 提供一种制造半导体器件的方法。 在具有栅极的基板上形成第一绝缘层和第二绝缘层。 执行间隔蚀刻工艺以形成蚀刻的第一绝缘层和蚀刻的第二绝缘层。 蚀刻的第一绝缘层从衬底部分地突出并接触栅极的侧壁。 蚀刻的第二绝缘层通过选择性外延生长（SEG）工艺去除，该工艺在暴露的衬底上形成外延层。 在蚀刻的第一绝缘层的突出部分上形成外延层的一个面。 第三绝缘层形成在蚀刻的第一绝缘层的侧壁上，并且外延层的一个面被第三绝缘层覆盖。

公开(公告)号：US20110003450A1

公开(公告)日：2011-01-06

申请号：US12646207

申请日：2009-12-23

Applicant: Young-Ho LEE ,  Tae-Hang Ahn ,  Seung-Beom Baek ,  Jun-Hee Cho ,  Jeong-Seon Kim

Inventor： Young-Ho LEE ,  Tae-Hang Ahn ,  Seung-Beom Baek ,  Jun-Hee Cho ,  Jeong-Seon Kim

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/78 ,  H01L29/7848

Abstract: A method for forming a semiconductor device includes forming a gate pattern over a silicon substrate, forming gate spacers over both sidewalls of the gate pattern, forming a dummy gate spacer over a sidewall of each one of the gate spacers, forming a recess region having inclined sidewalls extending in a direction to a channel region under the gate pattern by recess-etching the silicon substrate, filling the recess region with an epitaxial film, which becomes a source region or a drain region, through a selective epitaxial growth process, and removing the dummy gate spacer.

Abstract translation: 一种用于形成半导体器件的方法包括在硅衬底上形成栅极图案，在栅极图案的两个侧壁上形成栅极间隔物，在每个栅极间隔物的侧壁上形成虚拟栅极隔离物，形成具有倾斜 通过凹槽蚀刻硅衬底沿着栅极图案下方的沟道区域的方向延伸的侧壁，通过选择性外延生长工艺用成为源极区域或漏极区域的外延膜填充凹部区域， 虚拟栅极隔板。

公开(公告)号：US20140054787A1

公开(公告)日：2014-02-27

申请号：US13973627

申请日：2013-08-22

Applicant: Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

Inventor： Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

IPC: H01L23/498

CPC classification number: H01L23/498 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/441 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/49844 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

Abstract translation: 提供了形成由此制造的电极堆叠和三维半导体器件的方法。 该装置可以包括依次层叠在基板上以构成电极结构的电极。 每个电极可以包括从位于其上的一个电极的侧壁水平和向外突出的连接部分和具有与位于其上的电极之一的侧壁共面的对准部分。 这里，彼此垂直相邻设置的电极中的至少两个可以以这样的方式设置，使得其对准的部分具有基本上对准以彼此共面的侧壁。

公开(公告)号：US20120302024A1

公开(公告)日：2012-11-29

申请号：US13560577

申请日：2012-07-27

Applicant: Young-Ho LEE ,  Seung-Joon JEON ,  Tae-Hang AHN

Inventor： Young-Ho LEE ,  Seung-Joon JEON ,  Tae-Hang AHN

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.

Abstract translation: 半导体器件包括：衬底上的栅极图案; 在栅极图案的两侧设置在基板中的凹部图案，每个凹部图案具有在栅极图案下方延伸的侧表面; 以及填充凹陷图案的源极和漏极，并且在栅极图案下形成应变通道。

公开(公告)号：US20120252185A1

公开(公告)日：2012-10-04

申请号：US13470773

申请日：2012-05-14

Applicant: Young-Ho LEE ,  Jae-Kwan PARK ,  Jae-Hwang SIM ,  Sang-Yong PARK

Inventor： Young-Ho LEE ,  Jae-Kwan PARK ,  Jae-Hwang SIM ,  Sang-Yong PARK

IPC: H01L21/762 ,  H01L21/302 ,  H01L21/28

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。 间隔件形成在第一和第二掩模结构的相对侧壁上。 第一掩模结构被选择性地从第一区域中的间隔物之间​​移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案 在第二区域中。

公开(公告)号：US20100027734A1

公开(公告)日：2010-02-04

申请号：US12181891

申请日：2008-07-29

Applicant: Jae-Yong KIM ,  Hyung-Kyu KIM ,  Kyung-Ho YOON ,  Young-Ho LEE ,  Kang-Hee LEE

Inventor： Jae-Yong KIM ,  Hyung-Kyu KIM ,  Kyung-Ho YOON ,  Young-Ho LEE ,  Kang-Hee LEE

IPC: G21C3/34

CPC classification number: G21C3/02 ,  G21C3/322 ,  G21C3/352 ,  G21C3/356 ,  Y02E30/38

Abstract: A spacer grid for dual-cooling nuclear fuel rods arranged at a narrow interval. The spacer grid solves the problem in which, since the dual-cooling nuclear fuel rods are used to improve the cooling performance and stability of nuclear fuel and obtain high burnup and output, the outer diameter of each dual-cooling nuclear fuel rod is increased, and thus the gap between each dual-cooling nuclear fuel rod and the grid strap is decreased. The spacer grid includes first grid straps and second grid straps, which are crossed and arranged in transverse and longitudinal directions at regular intervals and have the shape of a flat strip, and support structures, which are fitted into the first and second grid straps around intersections of the first and second grid straps so as to support the dual-cooling nuclear fuel rods.

Abstract translation: 用于双冷却核燃料棒的隔离栅格，其间隔狭窄。 间隔栅格解决了由于双冷核燃料棒用于提高核燃料的冷却性能和稳定性并获得高燃耗和输出的问题，每个双重冷却核燃料棒的外径增加， 因此，每个双重冷却核燃料棒和网格带之间的间隙减小。 间隔网格包括第一网格带和第二网格带，它们以横向和纵向方向以规则的间隔交叉并布置，并且具有扁平条形状和支撑结构，其被安装在交叉点周​​围的第一和第二网格带中 的第一和第二格栅带，以支撑双重冷却核燃料棒。

公开(公告)号：US20090230085A1

公开(公告)日：2009-09-17

申请号：US12235034

申请日：2008-09-22

Applicant: Young-Ho LEE ,  Steve CHUN ,  Dek-Gin YANG ,  Chan-Yeup CHUNG ,  Yun-Seok HWANG ,  Keun-Ho KIM

Inventor： Young-Ho LEE ,  Steve CHUN ,  Dek-Gin YANG ,  Chan-Yeup CHUNG ,  Yun-Seok HWANG ,  Keun-Ho KIM

IPC: H01B13/34 ,  C09K13/00

CPC classification number: H05K3/385 ,  H05K3/389 ,  H05K3/44 ,  H05K2203/0307 ,  H05K2203/0315

Abstract: The present invention provides a composition for surface modification of a heat sink, the composition including: 0.01 to 10 parts by weight of an organic titanium compound; 0.01 to 5 parts by weight of an organic silane compound; 0.1 to 10 parts by weight of an organic acid; 0.01 to 5 parts by weight of a sequestering agent; and 0.1 to 10 parts by weight of a buffer with respect to 100 parts by weight of distilled water. The composition of the present invention provides excellent adhesion strength with prepreg, and improve heat releasing performance.

Abstract translation: 本发明提供了一种用于散热器表面改性的组合物，该组合物包括：0.01至10重量份的有机钛化合物; 0.01〜5重量份的有机硅烷化合物; 0.1〜10重量份的有机酸; 0.01〜5重量份的螯合剂; 相对于100重量份的蒸馏水为0.1〜10重量份的缓冲液。 本发明的组合物与预浸料提供优异的粘合强度，并且提高散热性能。

公开(公告)号：US20140197546A1

公开(公告)日：2014-07-17

申请号：US14156827

申请日：2014-01-16

Applicant: Sung-Min HWANG ,  Young-Ho LEE ,  Seong-Soon CHO ,  Woon-Kyung LEE

Inventor： Sung-Min HWANG ,  Young-Ho LEE ,  Seong-Soon CHO ,  Woon-Kyung LEE

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.

Abstract translation: 垂直型半导体器件中的阶形形状焊盘结构和布线结构包括具有第一线形状并且在边缘部分的上表面处包括第一焊盘区域的第一导线和具有第二线形并且间隔开的第二导线 并且设置在第一导线上。 第一导线的端部延伸到第一位置。 第二焊盘区域包括在第二导线的边缘部分的上表面上。 第二导线的端部延伸到第一位置。 第二导电线包括在垂直方向上与第一焊盘区域相对的部分处的凹部，以露出第一焊盘区域。 衬垫结构可以用在垂直型非易失性存储器件中。