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    Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area
    3.
    发明授权
    Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area 失效
    解决对准标记盲目问题的方法和在微小区域应用半导体蚀刻技术

    公开(公告)号：US06746966B1

    公开(公告)日：2004-06-08

    申请号：US10353229

    申请日：2003-01-28

    申请人： Chung-Long Chang ,  Henry Lo ,  Shang-Ting Tsai ,  Yu-Liang Lin

    发明人： Chung-Long Chang ,  Henry Lo ,  Shang-Ting Tsai ,  Yu-Liang Lin

    IPC分类号： H01L21302

    CPC分类号： H01L21/31111 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084

    摘要： A method of unblinding an alignment mark comprising the following steps. A substrate having a cell area and an alignment mark within an alignment area is provided. An STI trench is formed into the substrate within the cell area. A silicon oxide layer is formed over the substrate, filling the STI trench and the alignment mark. The silicon oxide layer is planarized to form a planarized STI within the STI trench and leaving silicon oxide within the alignment mark to form a blinded alignment mark. A wet chemical etchant is applied within the alignment mark area over the blinded alignment mark to at least partially remove the silicon oxide within the alignment mark. The remaining silicon oxide is removed from within the blinded alignment mark to unblind the alignment mark. A drop etcher apparatus is also disclosed.

    摘要翻译： 一种解开对准标记的方法，包括以下步骤。 提供了在对准区域内具有单元区域和对准标记的基板。 在沟槽区内形成STI沟槽。 在衬底上形成氧化硅层，填充STI沟槽和对准标记。 将氧化硅层平坦化以在STI沟槽内形成平坦化的STI，并使对准标记内的氧化硅形成盲目的对准标记。 湿法化学蚀刻剂施加在对准标记区域内的盲目对准标记上，以至少部分地去除对准标记内的氧化硅。 剩余的氧化硅从盲目的对准标记中移除，以对准对准标记。 还公开了一种滴蚀蚀刻装置。

    Advanced process control approach for Cu interconnect wiring sheet resistance control
    4.
    发明授权
    Advanced process control approach for Cu interconnect wiring sheet resistance control 失效
    Cu互连布线电阻控制的先进工艺控制方法

    公开(公告)号：US07083495B2

    公开(公告)日：2006-08-01

    申请号：US10723236

    申请日：2003-11-26

    申请人： Chun Hsien Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    发明人： Chun Hsien Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    IPC分类号： B24B49/00 ,  B24B1/00

    CPC分类号： B24B51/00 ,  B24B37/042 ,  G05B13/024 ,  H01L21/31053 ,  H01L21/3212

    摘要： A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3σ variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.

    摘要翻译： 描述了用于控制氧化物（Cu或TaN）抛光步骤的基于晶圆的APC方法，并且组合了用于补偿进入晶片变化的前馈模型与补偿CMP变化的馈送反向模型。 该方法面向最小化Rs 3sigma变化。 输入Rs目标值，其中来自先前工艺的测量数据影响铜层的宽度和厚度。 确定第一晶片的铜厚度目标和抛光时间。 第一晶片的CMP后测量数据被用于利用干扰因子修改抛光速率，并且为随后的晶片计算更新的抛光时间。 每个晶片的CMP配方用测量数据和后CMP测量进行调整。 APC方法成功地控制了90nm技术节点的铜Rs变化，并且与铜图案密度无关。

    Advanced process control approach for Cu interconnect wiring sheet resistance control
    6.
    发明申请
    Advanced process control approach for Cu interconnect wiring sheet resistance control 失效
    Cu互连布线电阻控制的先进工艺控制方法

    公开(公告)号：US20050112997A1

    公开(公告)日：2005-05-26

    申请号：US10723236

    申请日：2003-11-26

    申请人： Chun Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    发明人： Chun Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    IPC分类号： B24B37/04 ,  B24B51/00 ,  G05B13/02 ,  H01L21/3105 ,  H01L21/321 ,  B24B49/00 ,  B24B1/00

    CPC分类号： B24B51/00 ,  B24B37/042 ,  G05B13/024 ,  H01L21/31053 ,  H01L21/3212

    摘要： A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3σ variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.

    摘要翻译： 描述了用于控制氧化物（Cu或TaN）抛光步骤的基于晶圆的APC方法，并且组合了用于补偿进入晶片变化的前馈模型与补偿CMP变化的馈送反向模型。 该方法面向最小化Rs 3sigma变化。 输入Rs目标值，其中来自先前工艺的测量数据影响铜层的宽度和厚度。 确定第一晶片的铜厚度目标和抛光时间。 第一晶片的CMP后测量数据被用于利用干扰因子修改抛光速率，并且为随后的晶片计算更新的抛光时间。 每个晶片的CMP配方用测量数据和后CMP测量进行调整。 APC方法成功地控制了90nm技术节点的铜Rs变化，并且与铜图案密度无关。

    FIB exposure of alignment marks in MIM technology
    8.
    发明申请
    FIB exposure of alignment marks in MIM technology 审中-公开
    MIM技术中FIB曝光对准标记

    公开(公告)号：US20050186753A1

    公开(公告)日：2005-08-25

    申请号：US10786187

    申请日：2004-02-25

    申请人： Ping-Hsu Chen ,  Ping Chuang ,  Mei-Sheng Zhou ,  Francis Ko ,  Huxley Lee ,  Joshua Tseng ,  Henry Lo

    发明人： Ping-Hsu Chen ,  Ping Chuang ,  Mei-Sheng Zhou ,  Francis Ko ,  Huxley Lee ,  Joshua Tseng ,  Henry Lo

    IPC分类号： G03F9/00 ,  H01J37/304 ,  H01L21/302 ,  H01L21/461 ,  H01L21/76 ,  H01L23/544

    CPC分类号： H01L23/544 ,  G03F9/708 ,  G03F9/7084 ,  H01J37/3045 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A new and improved method for exposing alignment marks on a substrate by locally cutting through a metal or non-metal layer or layers sequentially deposited on the substrate above the alignment marks, using focused ion beam (FIB) technology. In a preferred embodiment, a method for exposing alignment marks on a substrate can be carried out by first providing a substrate that has multiple alignment marks provided thereon and at least one overlying opaque layer, typically but not necessarily metal, deposited on the substrate above the alignment marks. A focused ion beam is then directed against the overlying opaque layer or layers to cut through the layer or layers and expose the alignment marks on the substrate. A noble gas, preferably argon, is typically used as the ion source for the focused ion beam.

    摘要翻译： 一种新的和改进的方法，通过使用聚焦离子束（FIB）技术，通过局部切割穿过对准标记上方的基板上的金属或非金属层或层而在基板上曝光对准标记。 在优选实施例中，用于在衬底上曝光对准标记的方法可以通过首先提供其上设置有多个对准标记的衬底和沉积在衬底上方的至少一个上覆的不透明层（通常但不一定是金属） 对齐标记 然后将聚焦离子束定向到上覆的不透明层或层以切穿该层或者暴露衬底上的对准标记。 惰性气体，优选氩气通常用作聚焦离子束的离子源。

    System and method for dampening high pressure impact on porous materials
    9.
    发明授权
    System and method for dampening high pressure impact on porous materials 失效
    用于抑制高压冲击多孔材料的系统和方法

    公开(公告)号：US06875285B2

    公开(公告)日：2005-04-05

    申请号：US10422339

    申请日：2003-04-24

    申请人： Ching-Ya Wang ,  Ping Chuang ,  Yu-Liang Lin ,  Mei-Sheng Zhou ,  Henry Lo

    发明人： Ching-Ya Wang ,  Ping Chuang ,  Yu-Liang Lin ,  Mei-Sheng Zhou ,  Henry Lo

    IPC分类号： B08B7/00 ,  H01L21/306 ,  H01L21/311 ,  C23G1/00

    CPC分类号： H01L21/31116 ,  B08B7/0021 ,  H01L21/02052

    摘要： System and method for reducing damage to a semiconductor substrate when using cleaning fluids at elevated pressures to clean the semiconductor substrates. A preferred embodiment comprises applying the cleaning fluid at a first pressure for a first time period, wherein the first pressure is relatively low, and then increasing the pressure of the cleaning fluid to a pressure level that can effectively clean the semiconductor substrate and maintaining the pressure level for a second time period. The application of the cleaning fluid at the relatively low initial pressure acts as a temporary filler and creates a buffer of the cleaning fluid on the semiconductor substrate and helps to dampen the impact of the subsequent high pressure application of the cleaning fluid on the semiconductor substrate.

    摘要翻译： 当在高压下使用清洁流体以清洁半导体衬底时，减少对半导体衬底的损伤的系统和方法。 优选实施例包括在第一时间段内施加第一压力的清洁流体，其中第一压力相对较低，然后将清洁流体的压力提高到可以有效地清洁半导体衬底并保持压力的压力水平 水平第二次。 以相对较低的初始压力施加清洁流体作为临时填料并在半导体衬底上产生清洗液的缓冲液，并且有助于抑制随后的高压施加清洁流体对半导体衬底的冲击。

    Polishing pad conditioning disks for chemical mechanical polisher
    10.
    发明授权
    Polishing pad conditioning disks for chemical mechanical polisher 有权
    用于化学机械抛光机的抛光垫调节盘

    公开(公告)号：US06872127B2

    公开(公告)日：2005-03-29

    申请号：US10194894

    申请日：2002-07-11

    申请人： Yu-Liang Lin ,  Henry Lo ,  Ping Chuang

    发明人： Yu-Liang Lin ,  Henry Lo ,  Ping Chuang

    IPC分类号： B24B53/017 ,  B24B53/12 ,  B24B1/00

    CPC分类号： B24B53/017 ,  B24B53/12

    摘要： The invention relates to disks for conditioning pads used in the chemical mechanical polishing of semiconductor wafers, and a method of fabricating the pads. In one embodiment, the conditioning pad includes multiple, pyramid-shaped, truncated protrusions which are cut or shaped in the surface of a typically stainless steel substrate. Each of the truncated protrusions includes a plateau in the top thereof. A seed layer, typically titanium nitride (TiN), is provided on the surface of the protrusions, and a contact layer such as diamond-like carbon (DLC) or other suitable film is provided over the seed layer. In another embodiment, each of the protrusions is pyramid-shaped and includes a pointed apex at the top thereof.

    摘要翻译： 本发明涉及用于半导体晶片的化学机械抛光中的调节垫的盘及其制造方法。 在一个实施例中，调节垫包括在典型的不锈钢衬底的表面中切割或成形的多个金字塔形的截头突起。 每个截头突起在其顶部包括平台。 在突起的表面上提供种子层，通常为氮化钛（TiN），并且在种子层上提供诸如类金刚石碳（DLC）等接触层或其它合适的膜。 在另一个实施例中，每个突起是金字塔形的，并且在其顶部包括尖顶。