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    STI structure and method of forming bottom void in same
    1.
    发明授权
    STI structure and method of forming bottom void in same 有权
    STI结构和形成底部空隙的方法相同

    公开(公告)号：US08461015B2

    公开(公告)日：2013-06-11

    申请号：US12757203

    申请日：2010-04-09

    申请人： Yu-Lien Huang ,  Han-Pin Chung ,  Shiang-Bau Wang

    发明人： Yu-Lien Huang ,  Han-Pin Chung ,  Shiang-Bau Wang

    IPC分类号： H01L21/76 ,  H01L21/469

    CPC分类号： H01L21/76224

    摘要： A method for forming an STI structure is provided. In one embodiment, a trench is formed in a substrate, the trench having a first sidewall and a second sidewall opposite the first sidewall, the sidewalls extending down to a bottom portion of the trench. An insulating material is deposited to line the surfaces of the sidewalls and the bottom portion. The insulating material proximate the top portions and the bottom portion of the trench are thereafter etched back. The insulating material is deposited to line the inside surfaces of the trench at a rate sufficient to allow a first protruding insulating material deposited on the first sidewall and a second protruding insulating material deposited on the second sidewall to approach theretogether. The steps of etching back and depositing are repeated to have the first and second protruding materials abut, thereby forming a void near the bottom of the trench.

    摘要翻译： 提供了一种用于形成STI结构的方法。 在一个实施例中，在衬底中形成沟槽，沟槽具有第一侧壁和与第一侧壁相对的第二侧壁，所述侧壁向下延伸到沟槽的底部。 沉积绝缘材料以对侧壁和底部的表面进行排列。 此后，接近顶部和沟槽底部的绝缘材料被回蚀。 绝缘材料被沉积成以足以允许沉积在第一侧壁上的第一突出绝缘材料和沉积在第二侧壁上的第二突出绝缘材料一齐接近的速率对沟槽的内表面进行排列。 重复蚀刻回落和沉积的步骤以使第一和第二突出材料抵接，从而在沟槽的底部附近形成空隙。

    Method of dual EPI process for semiconductor device
    4.
    发明授权
    Method of dual EPI process for semiconductor device 有权
    半导体器件的双重EPI工艺方法

    公开(公告)号：US08609497B2

    公开(公告)日：2013-12-17

    申请号：US12721399

    申请日：2010-03-10

    申请人： Han-Pin Chung ,  Bor Chiuan Hsieh ,  Shiang-Bau Wang ,  Ming-Jie Huang

    发明人： Han-Pin Chung ,  Bor Chiuan Hsieh ,  Shiang-Bau Wang ,  Ming-Jie Huang

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823487 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.

    摘要翻译： 本公开提供一种制造半导体器件的方法，该半导体器件包括分别在衬底的第一和第二区域上形成第一和第二栅极结构，在第一和第二栅极结构的侧壁上形成间隔物，间隔物由第一材料形成 在所述第一和第二栅极结构上形成覆盖层，所述覆盖层由不同于所述第一材料的第二材料形成，在所述第二区域上形成保护层以保护所述第二栅极结构，在所述第一栅极结构上移除所述覆盖层 门结构; 在所述第二区域上去除所述保护层，在所述第一区域中外延（epi）在所述衬底的暴露部分上生长半导体材料，以及通过蚀刻工艺去除所述第二栅极结构上的所述覆盖层，所述蚀刻工艺显示所述第二区域的蚀刻选择性 材料到第一种材料。

    Method of Dual EPI Process For Semiconductor Device
    6.
    发明申请
    Method of Dual EPI Process For Semiconductor Device 有权
    半导体器件的双重EPI工艺方法

    公开(公告)号：US20110201164A1

    公开(公告)日：2011-08-18

    申请号：US12721399

    申请日：2010-03-10

    申请人： Han-Pin Chung ,  Bor Chiuan Hsieh ,  Shiang-Bau Wang ,  Ming-Jie Huang

    发明人： Han-Pin Chung ,  Bor Chiuan Hsieh ,  Shiang-Bau Wang ,  Ming-Jie Huang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823487 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.

    摘要翻译： 本公开提供一种制造半导体器件的方法，该半导体器件包括分别在衬底的第一和第二区域上形成第一和第二栅极结构，在第一和第二栅极结构的侧壁上形成间隔物，间隔物由第一材料形成 在所述第一和第二栅极结构上形成覆盖层，所述覆盖层由不同于所述第一材料的第二材料形成，在所述第二区域上形成保护层以保护所述第二栅极结构，在所述第一栅极结构上移除所述覆盖层 门结构; 在所述第二区域上去除所述保护层，在所述第一区域中外延（epi）在所述衬底的暴露部分上生长半导体材料，以及通过蚀刻工艺去除所述第二栅极结构上的所述覆盖层，所述蚀刻工艺显示所述第二区域的蚀刻选择性 材料到第一种材料。

    Post CMP planarization by cluster ion beam etch
    8.
    发明授权
    Post CMP planarization by cluster ion beam etch 有权
    通过簇离子束蚀刻后CMP平坦化

    公开(公告)号：US08604562B2

    公开(公告)日：2013-12-10

    申请号：US13466569

    申请日：2012-05-08

    申请人： Shiang-Bau Wang

    发明人： Shiang-Bau Wang

    IPC分类号： H01L29/00

    CPC分类号： H01L21/31055 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/76229 ,  H01L21/76819 ,  H01L22/12 ,  H01L22/20

    摘要： The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GCIB) etch tool to determine how much film to remove on a particular location. GCIB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies.

    摘要翻译： 所描述的机构的实施例使得能够改善衬底的平面性，这对于图案化和器件产量提高至关重要。 在达到最终厚度之前或在所有去除膜被抛光之前，使用化学机械抛光（CMP）去除膜以使基板平坦化。 然后测量衬底的形貌和膜厚度。 气体簇离子束（GCIB）蚀刻工具使用地形和厚度数据来确定在特定位置上要移除多少胶片。 GCIB蚀刻可以去除最终层，以满足基板均匀性和厚度目标的要求。 这些机制可以提高平面性，以满足先进的处理技术的要求。

    Hard mask removal method
    9.
    发明授权
    Hard mask removal method 有权
    硬掩模去除方法

    公开(公告)号：US08361338B2

    公开(公告)日：2013-01-29

    申请号：US12704032

    申请日：2010-02-11

    申请人： Shiang-Bau Wang

    发明人： Shiang-Bau Wang

    IPC分类号： C23F1/00 ,  B44C1/22

    CPC分类号： H01L21/02107 ,  H01L21/02071 ,  H01L21/02697 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32139

    摘要： The embodiments of methods described in this disclosure for removing a hard mask layer(s) over a polysilicon layer of a gate stack after the gate stack is etched allows the complete removal of the hard mask layer without the assistance of photolithography. A dielectric material is deposited over the substrate with the gate stacks. The topography of the substrate is removed by chemical mechanical polishing first. Afterwards, an etching gas (or vapor) is used to etch a portion of the remaining dielectric layer and the hard mask layer. The etching gas forms an etch byproduct that deposits on the substrate surface and can be subsequently removed by heating. The etching and heating to remove etch byproduct are repeated until the hard mask layer is completed removed. Afterwards, the remaining dielectric layer is removed by wet etch. The methods described are simpler and cheaper to use than conventional methods for hard mask removal.

    摘要翻译： 在本公开中描述的用于在蚀刻栅极叠层之后去除栅极堆叠的多晶硅层上的硬掩模层的方法的实施例允许在没有光刻的帮助下完全去除硬掩模层。 电介质材料沉积在衬底上，栅极叠层。 首先通过化学机械抛光去除衬底的形貌。 之后，使用蚀刻气体（或蒸汽）来蚀刻剩余介电层和硬掩模层的一部分。 蚀刻气体形成沉积在衬底表面上的蚀刻副产物，随后可通过加热除去。 重复蚀刻和加热去除蚀刻副产物，直到硬掩模层完成去除。 之后，通过湿蚀刻除去剩余的介电层。 与常规的硬掩模去除方法相比，所描述的方法更简单并且更便宜。

    END-TO-END GAP FILL USING DIELECTRIC FILM
    10.
    发明申请
    END-TO-END GAP FILL USING DIELECTRIC FILM 有权
    使用电介质膜的端到端胶带填充

    公开(公告)号：US20120205746A1

    公开(公告)日：2012-08-16

    申请号：US13025414

    申请日：2011-02-11

    申请人： Shiang-Bau Wang

    发明人： Shiang-Bau Wang

    IPC分类号： H01L27/088 ,  H01L21/28

    CPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/76837

    摘要： A method for fabricating a semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. The plurality of gate structures are arranged in a plurality of lines, wherein an end-to-end spacing between the lines is smaller than a line-to-line spacing between the lines. The method further includes forming an etch stop layer over the gate structures, forming an interlayer dielectric over the gate structures, and forming a dielectric film over the gate structures before the interlayer dielectric is formed. The dielectric film merges in end-to-end gaps formed in the end-to-end spacing between the gate structures.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成多个栅极结构。 多个栅极结构被布置成多条线，其中线之间的端对端间隔小于线之间的线间间隔。 该方法还包括在栅极结构上形成蚀刻停止层，在栅极结构之上形成层间电介质，以及在形成层间电介质之前在栅极结构上形成电介质膜。 电介质膜在形成在门结构之间的端到端间隔中的端到端间隙中融合。