公开(公告)号：US5744826A

公开(公告)日：1998-04-28

申请号：US785952

申请日：1997-01-22

申请人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata

发明人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/12 ,  H01L29/24 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/7813 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/0696 ,  H01L29/1608 ,  Y10S438/931

摘要： A semiconductor substrate 4 consisting of an n.sup.+ -type substrate 1, an n.sup.- -type silicon carbide semiconductor layer 2 and a p-type silicon carbide semiconductor layer 3, made of hexagonal crystal-based single crystal silicon carbide with the main surface having a planar orientation approximately in the (0001) carbon face. An n.sup.+ -type source region 5 is formed in the surface layer of the semiconductor layer 3, and a trench 7 runs from the main surface through the region 5 and the semiconductor layer 3 reaching to the semiconductor layer 2, and extending approximately in the �1120! direction. An n-type silicon carbide semiconductor thin-film layer 8 is provided on the region 5, the semiconductor layer 3 and the semiconductor layer 2 on the side walls of the trench 7, while a gate electrode layer 10 is formed on the inner side of a gate insulating film 9, a source electrode layer 12 is formed on the surface of the semiconductor region 5, and a drain electrode layer 13 is formed on the surface of the n.sup.+ -type substrate 1.

摘要翻译： 由n +型基板1，n型碳化硅半导体层2和p型碳化硅半导体层3构成的半导体基板4由六面晶体型单晶碳化硅制成，主表面具有 大概在（000 + E，ovs 1 + EE）碳面的平面取向。 在半导体层3的表面层中形成n +型源极区域5，并且沟槽7从主表面延伸穿过半导体层2的区域5和半导体层3，并且大致在[ 11 + E，ovs 2 + EE 0]方向。 在沟槽7的侧壁上的区域5，半导体层3和半导体层2上设置n型碳化硅半导体薄膜层8，而在栅极电极层10的内侧形成有栅电极层10 栅极绝缘膜9，在半导体区域5的表面上形成源电极层12，在n +型衬底1的表面上形成漏电极层13。

公开(公告)号：US6133587A

公开(公告)日：2000-10-17

申请号：US23280

申请日：1998-02-13

申请人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata ,  Takamasa Suzuki ,  Shoichi Onda

发明人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata ,  Takamasa Suzuki ,  Shoichi Onda

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/0696

摘要： A n.sup.- -type source region 5 is formed on a predetermined region of the surface layer section of the p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4. A low-resistance p-type silicon carbide region 6 is formed on a predetermined region of the surface layer section in the p-type silicon carbide semiconductor layer 3. A trench 7 is formed in a predetermined region in the n.sup.+ -type source region 5, which trench 7 passes through the n.sup.+ -type source region 5 and the p-type silicon carbide semiconductor layer 3, reaching the n.sup.- -type silicon carbide semiconductor layer 2. The trench 7 has side walls 7a perpendicular to the surface of the semiconductor substrate 4 and a bottom side 7b parallel to the surface of the semiconductor substrate 4. The hexagonal region surrounded by the side walls 7a of the trench 7 is an island semiconductor region 12. A high-reliability gate insulating film 8 is obtained by forming a gate insulating layer on the side walls 7a which surround the island semiconductor region 12.

摘要翻译： n型源极区5形成在半导体衬底4的p型碳化硅半导体层3的表层部分的预定区域上。低电阻p型碳化硅区6形成在 在p型碳化硅半导体层3中的表层部分的预定区域。沟槽7形成在n +型源极区域5中的预定区域中，沟槽7通过n +型源极区域5，并且 p型碳化硅半导体层3，到达n型碳化硅半导体层2.沟槽7具有垂直于半导体衬底4的表面的侧壁7a和平行于半导体衬底的表面的底侧7b 由沟槽7的侧壁7a包围的六边形区域是岛状半导体区域12.通过在侧壁7a上形成栅极绝缘层，形成高可靠性栅极绝缘膜8， 岛半导体区域12。

公开(公告)号：US5976936A

公开(公告)日：1999-11-02

申请号：US893221

申请日：1997-07-15

申请人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

发明人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

IPC分类号： H01L21/04 ,  H01L29/08 ,  H01L29/24 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66068 ,  H01L29/7828 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/4236 ,  Y10S438/981

摘要： A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9.

摘要翻译： 提供了具有高阻断电压，低损耗和低阈值电压的碳化硅半导体器件。 n +型碳化硅半导体衬底1，n型碳化硅半导体衬底2和p型碳化硅半导体层3相互层叠在一起。 在p型碳化硅半导体层3的表面的预定区域中形成n +型源极区6，并且形成沟槽9，以延伸穿过n +型源极区6和p型碳化硅半导体层 在n型碳化硅半导体层2的表面上延伸设置有薄膜半导体层（n型或p型）11a，在n +型源极区6，p型碳化硅半导体层3的表面上， n型碳化硅半导体层2在沟槽9的侧面。

公开(公告)号：US6020600A

公开(公告)日：2000-02-01

申请号：US938805

申请日：1997-09-26

申请人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

发明人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

IPC分类号： H01L21/04 ,  H01L29/08 ,  H01L29/24 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/66068 ,  H01L29/7828 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/4236 ,  Y10S438/981

摘要： A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9. A gate electrode layer 13 is disposed through a gate insulating layer 12 within the trench 9. A source electrode layer 15 is provided on the surface of the p type silicon carbide semiconductor layer 3 and on the surface of the n.sup.+ type source region 6, and a drain electrode layer 16 is provided on the surface of the n.sup.+ type silicon carbide semiconductor substrate 1.

摘要翻译： 提供了具有高阻断电压，低损耗和低阈值电压的碳化硅半导体器件。 n +型碳化硅半导体衬底1，n型碳化硅半导体衬底2和p型碳化硅半导体层3相互层叠在一起。 在p型碳化硅半导体层3的表面的预定区域中形成n +型源极区6，并且形成沟槽9，以延伸穿过n +型源极区6和p型碳化硅半导体层 在n型碳化硅半导体层2的表面上延伸设置有薄膜半导体层（n型或p型）11a，在n +型源极区6，p型碳化硅半导体层3的表面上， 在沟槽9的侧面中的n型碳化硅半导体层2.栅极电极层13通过沟槽9内的栅极绝缘层12设置。源电极层15设置在p型表面上 碳化硅半导体层3和n +型源极区6的表面，以及在n +型碳化硅半导体衬底1的表面上设置漏电极层16。

公开(公告)号：US5915180A

公开(公告)日：1999-06-22

申请号：US418147

申请日：1995-04-05

申请人： Kazukuni Hara ,  Norihito Tokura ,  Takeshi Miyajima ,  Hiroo Fuma ,  Hiroyuki Kano

发明人： Kazukuni Hara ,  Norihito Tokura ,  Takeshi Miyajima ,  Hiroo Fuma ,  Hiroyuki Kano

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  Y10S438/931

摘要： A semiconductor device, which has an oxide laver with the thickness thereof being varied from portion to portion of the inner surface of a trench and can be easily produced, and a process of producing the same. An n.sup.+ type single crystal SiC substrate is formed of SiC of hexagonal system having a carbon face with a (0001) face orientation as a surface, and an n type epitaxial layer and a p type epitaxial layer are successively laminated onto the substrate. An n.sup.+ source region is provided within the p type epitaxial layer, and the trench extends through the source region and the epitaxial layer into the semiconductor substrate. The side face of the trench is almost perpendicular to the surface of the epitaxial layer with the bottom face of the trench having a plane parallel to the surface of the epitaxial layer. The thickness of a gate oxide layer, formed by thermal oxidation, on the bottom face of the trench is larger than the thickness of the gate oxide layer on the side face of the trench. A gate electrode layer is provided on the surface of the oxide layer, formed by thermal oxidation, within the trench, a source electrode layer is provided on the epitaxial layer and the source region, and a drain electrode layer is provided on the back surface of the semiconductor substrate.

摘要翻译： 具有其厚度的氧化物紫菜的半导体器件可以从沟槽的内表面的一部分变化，并且可以容易地制造，以及其制造方法。 n +型单晶SiC衬底由具有（0001）面取向的碳面作为表面的六方晶系的SiC形成，并且n型外延层和p型外延层依次层叠在衬底上。 在p型外延层内提供n +源极区，并且沟槽延伸穿过源区和外延层进入半导体衬底。 沟槽的侧面几乎垂直于外延层的表面，沟槽的底面具有平行于外延层的表面的平面。 在沟槽的底面上通过热氧化形成的栅极氧化物层的厚度大于沟槽侧面上的栅极氧化物层的厚度。 在氧化层形成的氧化层的表面上，在沟槽内设置栅极电极层，在外延层和源极区域设置有源电极层，在其背面设有漏电极层 半导体衬底。

公开(公告)号：US5723376A

公开(公告)日：1998-03-03

申请号：US745958

申请日：1996-11-07

申请人： Yuuichi Takeuchi ,  Takeshi Miyajima ,  Kazukuni Hara ,  Norihito Tokura

发明人： Yuuichi Takeuchi ,  Takeshi Miyajima ,  Kazukuni Hara ,  Norihito Tokura

IPC分类号： H01L21/04 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L29/7813 ,  H01L21/049 ,  H01L29/42368 ,  H01L29/66068 ,  Y10S438/931

摘要： A groove is formed on the surface of a semiconductor substrate composed of silicon carbide and a first thermal oxidation film is formed by executing thermal oxidation on a damaged layer of groove inner walls. Then, the first thermal oxidation film is removed so that the damaged layer can be removed. Since a second thermal oxidation film is formed after the damaged layer is removed, the second thermal oxidation film is uniform. A silicon carbide semiconductor device can be achieved with less side etching because substantially a (0001) carbon face of a cubic system is chosen as the plane orientation of the semiconductor substrate.

摘要翻译： 在由碳化硅构成的半导体基板的表面上形成有槽，通过对凹槽内壁的损伤层进行热氧化而形成第一热氧化膜。 然后，去除第一热氧化膜，从而可以去除损伤层。 由于在损坏层被去除之后形成第二热氧化膜，所以第二热氧化膜是均匀的。 可以通过较少的侧面蚀刻实现碳化硅半导体器件，因为基本上选择立方晶系的（0001）碳面作为半导体衬底的平面取向。

公开(公告)号：US6133120A

公开(公告)日：2000-10-17

申请号：US704820

申请日：1996-08-28

申请人： Takeshi Miyajima ,  Norihito Tokura ,  Atsuo Fukumoto ,  Hidemitsu Hayashi

发明人： Takeshi Miyajima ,  Norihito Tokura ,  Atsuo Fukumoto ,  Hidemitsu Hayashi

IPC分类号： H01L21/205 ,  C30B25/00 ,  C30B25/02 ,  H01L21/04 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L29/12 ,  H01L29/24 ,  H01L29/78 ,  C01B31/36

CPC分类号： H01L29/7813 ,  C30B25/00 ,  C30B25/02 ,  C30B29/36 ,  H01L21/0455 ,  H01L29/66068 ,  H01L29/1608 ,  Y10S438/931

摘要： A p-type silicon carbide semiconductor having a high carrier concentration and activation rate is provided by doping boron as an acceptor impurity in a single crystal silicon carbide. The boron occupies silicon sites in a crystal lattice of the single crystal silicon carbide.

摘要翻译： 通过在单晶碳化硅中掺杂硼作为受主杂质来提供具有高载流子浓度和活化速率的p型碳化硅半导体。 硼占据单晶碳化硅的晶格中的硅位置。

公开(公告)号：US5696396A

公开(公告)日：1997-12-09

申请号：US734132

申请日：1996-10-21

申请人： Norihito Tokura ,  Kunihiko Hara ,  Takeshi Miyajima

发明人： Norihito Tokura ,  Kunihiko Hara ,  Takeshi Miyajima

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L29/24 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76 ,  H01L31/0312 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/7802

摘要： A vertical MOSFET, which can control AC current flowing through a device only by the gate voltage, is obtained. On an n.sup.+ silicon layer is formed an n.sup.- silicon layer. Within the n.sup.- silicon layer is formed a p-body region. Within the p-body region is formed an n.sup.+ source region. On top of a substrate are formed a source electrode in contact only with the source region and a base electrode in contact only with the p-body region. The source electrode and the base electrode are connected to each other through a resistance at the outside. On a channel region is formed a gate electrode through a gate oxide film (insulating film). When the above semiconductor device is in the reverse bias conduction, the exciting current is controlled only by the gate voltage by setting the current flowing from a source terminal through the resistance to the base electrode, the p-body region and the n.sup.- silicon layer to be negligibly small as compared with the current flowing from the source terminal through the source electrode to the n.sup.+ source region, the channel region and the n.sup.- silicon layer.

摘要翻译： 可以获得只能通过栅极电压控制流过器件的交流电流的垂直MOSFET。 在n +硅层上形成n-硅层。 在n-硅层内形成p体区域。 在p体区内形成n +源区。 在基板顶部形成仅与源极区域接触的源极电极和仅与p体区域接触的基极电极。 源电极和基极通过外部的电阻彼此连接。 在沟道区域上通过栅极氧化膜（绝缘膜）形成栅电极。 当上述半导体器件处于反向偏压传导时，通过将从源极端子流过电流的电流设置到基极，p体区域和n-硅层，从而仅通过栅极电压来控制励磁电流 与源极端子通过源极电极流到n +源极区域，沟道区域和n-硅层的电流相比，可以忽略不计。

公开(公告)号：US08018028B2

公开(公告)日：2011-09-13

申请号：US12980573

申请日：2010-12-29

申请人： Takeshi Miyajima

发明人： Takeshi Miyajima

IPC分类号： H01L29/866

CPC分类号： H01L29/7811 ,  H01L29/04 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/404 ,  H01L29/7808 ,  H01L29/7813 ,  H01L29/866 ,  Y10S438/931 ,  Y10S438/983

摘要： A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of the cell region. The Zener diode is disposed on the insulator film for electrically connecting the field plate with the outermost peripheral ring. The Zener diode has a first conductivity type region and a second conductivity type region that are alternately arranged in a direction from the cell region to the outer peripheral region.

公开(公告)号：US20080038850A1

公开(公告)日：2008-02-14

申请号：US11889075

申请日：2007-08-09

申请人： Hitoshi Yamaguchi ,  Takeshi Miyajima

发明人： Hitoshi Yamaguchi ,  Takeshi Miyajima

IPC分类号： H01L21/336 ,  H01L21/66

CPC分类号： H01L29/7813 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  Y10S438/977

摘要： A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.

摘要翻译： 半导体器件的制造方法包括：在半导体衬底上形成多个沟槽; 在每个沟槽中形成第二导电类型的半导体膜，以提供具有在两个沟槽之间的衬底的第一柱和在沟槽中的第二导电型半导体膜的第二柱，第一和第二列与预定方向交替地重复; 减薄基板的第二面; 并增加稀薄第二侧的杂质浓度，从而提供第一导电类型层。 第一导电型层的杂质浓度比第一列高。 第一列提供漂移层，从而形成垂直型第一导电型沟道晶体管。