公开(公告)号：US06787433B2

公开(公告)日：2004-09-07

申请号：US10246629

申请日：2002-09-19

申请人： Yuichiro Mitani ,  Yukie Nishikawa

发明人： Yuichiro Mitani ,  Yukie Nishikawa

IPC分类号： H01L2120

CPC分类号： H01L21/02609 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/2022 ,  H01L21/28017 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/76262 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/66772 ,  H01L29/78675

摘要： A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在非晶半导体层上沉积通过外延生长以预定晶面取向取向的晶体绝缘层，在所述晶体绝缘层上沉积第二非晶半导体层的步骤， 使用所述结晶绝缘膜作为芯将所述第一和第二半导体层生长成固相的多晶或单晶层，以及形成包含所述第一和第二半导体层的功能元件的步骤。

公开(公告)号：US07015121B2

公开(公告)日：2006-03-21

申请号：US10910578

申请日：2004-08-04

申请人： Yuichiro Mitani ,  Yukie Nishikawa

发明人： Yuichiro Mitani ,  Yukie Nishikawa

IPC分类号： H01L21/20

CPC分类号： H01L21/02609 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/2022 ,  H01L21/28017 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/76262 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/66772 ,  H01L29/78675

摘要： A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.

公开(公告)号：US20050009306A1

公开(公告)日：2005-01-13

申请号：US10910578

申请日：2004-08-04

申请人： Yuichiro Mitani ,  Yukie Nishikawa

发明人： Yuichiro Mitani ,  Yukie Nishikawa

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L27/10

CPC分类号： H01L21/02609 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/2022 ,  H01L21/28017 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/76262 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/66772 ,  H01L29/78675

摘要： A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在非晶半导体层上沉积通过外延生长以预定晶面取向取向的晶体绝缘层，在所述晶体绝缘层上沉积第二非晶半导体层的步骤， 使用所述结晶绝缘膜作为芯将所述第一和第二半导体层生长成固相的多晶或单晶层，以及形成包含所述第一和第二半导体层的功能元件的步骤。

公开(公告)号：US08916848B2

公开(公告)日：2014-12-23

申请号：US13598305

申请日：2012-08-29

申请人： Shosuke Fujii ,  Daisuke Matsushita ,  Yuichiro Mitani

发明人： Shosuke Fujii ,  Daisuke Matsushita ,  Yuichiro Mitani

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC分类号： H01L45/08 ,  G11C13/0007 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145

摘要： According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode.

摘要翻译： 根据一个实施例，电阻改变装置包括在第一和第二电极之间包括金属，第二电极和包括Si和O的无定形氧化物层的第一电极，具有浓度梯度为O的层和其第一峰值 在从第一电极到第二电极的方向上。

公开(公告)号：US08592892B2

公开(公告)日：2013-11-26

申请号：US11898603

申请日：2007-09-13

申请人： Yuichiro Mitani ,  Masahiro Koike ,  Yasushi Nakasaki ,  Daisuke Matsushita

发明人： Yuichiro Mitani ,  Masahiro Koike ,  Yasushi Nakasaki ,  Daisuke Matsushita

IPC分类号： H01L29/66

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/792

摘要： A nonvolatile semiconductor memory device includes: a memory element, the memory element including: a semiconductor substrate; a first insulating film formed on a region in the semiconductor substrate located between a source region and a drain region, and having a stack structure formed with a first insulating layer, a second insulating layer, and a third insulating layer in this order, the first insulating layer including an electron trapping site, the second insulating layer not including the electron trapping site, and the third insulating layer including the electron trapping site, and the electron trapping site being located in a position lower than conduction band minimum of the first through third insulating layers while being located in a position higher than conduction band minimum of a material forming the semiconductor substrate; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.

摘要翻译： 非易失性半导体存储器件包括：存储元件，所述存储元件包括：半导体衬底; 第一绝缘膜，形成在位于源区和漏区之间的半导体衬底的区域上，并且具有依次形成有第一绝缘层，第二绝缘层和第三绝缘层的堆叠结构，第一绝缘膜 包含电子俘获位置的绝缘层，不包含电子俘获位置的第二绝缘层和包含电子捕获位点的第三绝缘层，并且电子捕获位点位于低于第一至第三区域的导带最小值的位置 绝缘层位于高于形成半导体衬底的材料的导带最小值的位置; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制栅电极。

公开(公告)号：US08476718B2

公开(公告)日：2013-07-02

申请号：US12710851

申请日：2010-02-23

申请人： Izumi Hirano ,  Yuichiro Mitani ,  Tatsuo Shimizu ,  Yasushi Nakasaki ,  Akiko Masada ,  Shigeto Fukatsu ,  Masahiro Koike

发明人： Izumi Hirano ,  Yuichiro Mitani ,  Tatsuo Shimizu ,  Yasushi Nakasaki ,  Akiko Masada ,  Shigeto Fukatsu ,  Masahiro Koike

IPC分类号： H01L21/02

CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm−3 to 2.96×1020 cm−3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.

摘要翻译： 半导体器件包括：MISFET，包括：半导体层，包括形成在其中的半导体区域; 形成在所述半导体区域上方的栅极绝缘膜，并且包括含有金属和氧的金属氧化物层，所述金属氧化物层中所含的金属为选自Hf和Zr中的至少一种，所述金属氧化物层还包含至少一种元素 选自Ru，Cr，Os，V，Tc和Nb的金属氧化物层，金属氧化物层具有捕获或释放由元素包含形成的电荷的部位，金属氧化物层中的元素的密度在该范围内 1×1015cm-3至2.96×1020cm-3，这些位置被分配成具有比金属氧化物层的中心更靠近半导体区域的峰; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US08426302B2

公开(公告)日：2013-04-23

申请号：US13370532

申请日：2012-02-10

申请人： Daisuke Matsushita ,  Koichi Kato ,  Yuichiro Mitani

发明人： Daisuke Matsushita ,  Koichi Kato ,  Yuichiro Mitani

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7926 ,  G11C16/0466 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02312 ,  H01L21/28282 ,  H01L21/32105 ,  H01L27/11582 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78678

摘要： A method of manufacturing a semiconductor device according to an embodiment, includes: forming a stack structure by alternately stacking control gate electrodes and interlayer insulating films; forming a through-hole that penetrates through the stack structure in a stacking direction of the control gate electrodes and the interlayer insulating films; forming a first insulating film that covers an inner surface of the through-hole; forming a charge storage layer that covers an inner surface of the first insulating film; forming a second insulating film that covers an inner surface of the charge storage layer; forming a semiconductor layer that covers an inner surface of the second insulating film; and oxidizing an interface between the semiconductor layer and the second insulating film by performing a heat treatment in an atmosphere containing O2 gas at a temperature of 600° C. or lower.

摘要翻译： 根据实施例的制造半导体器件的方法包括：通过交替堆叠控制栅电极和层间绝缘膜形成堆叠结构; 在所述控制栅电极和所述层间绝缘膜的堆叠方向上形成穿过所述堆叠结构的通孔; 形成覆盖所述通孔的内表面的第一绝缘膜; 形成覆盖所述第一绝缘膜的内表面的电荷存储层; 形成覆盖所述电荷存储层的内表面的第二绝缘膜; 形成覆盖所述第二绝缘膜的内表面的半导体层; 在600℃以下的温度下，在含有O 2气体的气氛中进行热处理，氧化半导体层与第二绝缘膜的界面。

公开(公告)号：US20110003481A1

公开(公告)日：2011-01-06

申请号：US12801912

申请日：2010-07-01

申请人： Daisuke Matsushita ,  Koichi Muraoka ,  Koichi Kato ,  Yasushi Nakasaki ,  Yuichiro Mitani

发明人： Daisuke Matsushita ,  Koichi Muraoka ,  Koichi Kato ,  Yasushi Nakasaki ,  Yuichiro Mitani

IPC分类号： H01L21/314

CPC分类号： H01L27/11568 ,  C23C8/02 ,  C23C8/24 ,  C23C8/80 ,  H01L21/2652 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/28273 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/105 ,  H01L29/513

摘要： It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.

摘要翻译： 可以抑制成膜时的缺陷的产生。 一种制造半导体器件的方法，包括：将半导体衬底放置在大气中，从而在所述半导体衬底的表面上形成氮化物膜，所述气氛包含氮化所述半导体衬底的表面的第一氮化气体和第一稀释气体 实际上不与半导体衬底反应，第一稀释气体的分压和第一氮化气体的分压与第一氮化气体的分压之和的比率为5以上， 气氛为40乇或更低。

公开(公告)号：US07749919B2

公开(公告)日：2010-07-06

申请号：US11896860

申请日：2007-09-06

申请人： Kiwamu Sakuma ,  Daisuke Matsushita ,  Koichi Kato ,  Yasushi Nakasaki ,  Izumi Hirano ,  Kouichi Muraoka ,  Yuichiro Mitani ,  Shigeto Fukatsu ,  Toshihide Ito

发明人： Kiwamu Sakuma ,  Daisuke Matsushita ,  Koichi Kato ,  Yasushi Nakasaki ,  Izumi Hirano ,  Kouichi Muraoka ,  Yuichiro Mitani ,  Shigeto Fukatsu ,  Toshihide Ito

IPC分类号： H01L21/321

CPC分类号： H01L21/28273

摘要： A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.

摘要翻译： 半导体器件包括：半导体衬底; 在半导体衬底中形成为彼此间隔一定距离的源极区域和漏极区域; 形成在半导体衬底的一部分上的第一绝缘膜，该部分位于源区和漏区之间; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上方并由高介电常数材料制成的第二绝缘膜; 形成在所述第二绝缘膜上方的控制栅电极; 和包含具有三配位氮键的氮原子的氮化硅层，氮原子的第二最近邻原子中的至少一个为氮原子。 电荷存储膜和控制栅电极中的至少一个包含硅，氮化硅层位于第二绝缘膜和电荷存储膜和控制栅电极中的至少一个之间。

公开(公告)号：US07279737B2

公开(公告)日：2007-10-09

申请号：US11078313

申请日：2005-03-14

申请人： Akiko Nara ,  Masahiro Koike ,  Yuichiro Mitani

发明人： Akiko Nara ,  Masahiro Koike ,  Yuichiro Mitani

IPC分类号： H01L29/788

CPC分类号： H01L21/28194 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7883

摘要： A nonvolatile semiconductor memory device includes a gate electrode portion composed of a floating gate electrode formed above a main surface of a semiconductor substrate of a first conductivity type via a tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode and formed of a stacked structure film of three or more layers formed of two or more types of high-dielectric material, and a control gate electrode formed above the floating gate electrode via the inter-electrode insulating film, and source and drain regions of a second conductivity type which are formed on the main surface of the substrate with the gate electrode portion being arranged between the source and drain regions.

摘要翻译： 非易失性半导体存储器件包括：栅极电极部分，其由通过隧道绝缘膜形成在第一导电类型的半导体衬底的主表面上方的浮栅电极组成;电极间绝缘膜，形成在浮栅电极上，形成 由两种或更多种类型的高介电材料形成的三层或更多层的叠层结构膜，以及通过所述电极间绝缘膜形成在所述浮栅上的控制栅极，以及第二导电性的源极和漏极区 型，其形成在基板的主表面上，栅电极部分布置在源区和漏区之间。