Image encoding apparatus and control method thereof
    1.
    发明授权
    Image encoding apparatus and control method thereof 有权
    图像编码装置及其控制方法

    公开(公告)号:US08577096B2

    公开(公告)日:2013-11-05

    申请号:US12634256

    申请日:2009-12-09

    IPC分类号: G06K9/34

    摘要: An encoding apparatus encodes an image by tile in a smallest possible size while suppresses segmentation of a specific region in the image into tiles. Vertical lines at left and right ends of n-th face region are defined as boundary candidate vertical lines Lh(n) and Lm(n), and horizontal lines at upper and lower ends of the n-th region, as boundary candidate horizontal lines Lu(n) and Ls(n). A divider determines a horizontal line of another region existing within the range of the horizontal lines Lu(n) and Ls(n) of the n-th region as a line to be deleted. Further, the divider determines a vertical line of another region existing within the range of the vertical lines Lh(n) and Lm(n) as a line to be deleted. This processing is performed to the final region, then image data is divided using horizontal and vertical lines except the lines determined as lines to be deleted.

    摘要翻译: 编码装置以最小的可能尺寸对图像进行编码,同时抑制将图像中的特定区域分割为瓦片。 第n个面区域的左右端的垂直线被定义为边界候选垂直线Lh(n)和Lm(n),第n个区域的上端和下端的水平线作为边界候选水平线 Lu(n)和Ls(n)。 分割器确定存在于作为要删除的行的第n个区域的水平线Lu(n)和Ls(n)的范围内的另一区域的水平线。 此外,分割器确定存在于垂直线Lh(n)和Lm(n)的范围内的另一区域的垂直线作为要删除的线。 对最终区域执行该处理,然后使用除了被确定为要删除的行的行之外的水平和垂直线分割图像数据。

    IMAGE ENCODING APPARATUS AND CONTROL METHOD THEREOF
    2.
    发明申请
    IMAGE ENCODING APPARATUS AND CONTROL METHOD THEREOF 有权
    图像编码装置及其控制方法

    公开(公告)号:US20100158401A1

    公开(公告)日:2010-06-24

    申请号:US12634256

    申请日:2009-12-09

    IPC分类号: G06K9/46

    摘要: An encoding apparatus encodes an image by tile in a smallest possible size while suppresses segmentation of a specific region in the image into tiles. Vertical lines at left and right ends of n-th face region are defined as boundary candidate vertical lines Lh(n) and Lm(n), and horizontal lines at upper and lower ends of the n-th region, as boundary candidate horizontal lines Lu(n) and Ls(n). A divider determines a horizontal line of another region existing within the range of the horizontal lines Lu(n) and Ls(n) of the n-th region as a line to be deleted. Further, the divider determines a vertical line of another region existing within the range of the vertical lines Lh(n) and Lm(n) as a line to be deleted. This processing is performed to the final region, then image data is divided using horizontal and vertical lines except the lines determined as lines to be deleted.

    摘要翻译: 编码装置以最小的可能尺寸对图像进行编码,同时抑制将图像中的特定区域分割为瓦片。 第n个面区域的左右端的垂直线被定义为边界候选垂直线Lh(n)和Lm(n),第n个区域的上端和下端的水平线作为边界候选水平线 Lu(n)和Ls(n)。 分割器确定存在于作为要删除的行的第n个区域的水平线Lu(n)和Ls(n)的范围内的另一区域的水平线。 此外,分割器确定存在于垂直线Lh(n)和Lm(n)的范围内的另一区域的垂直线作为要删除的线。 对最终区域执行该处理,然后使用除了被确定为要删除的行的行之外的水平和垂直线分割图像数据。

    Information processing apparatus, information processing method, and program
    3.
    发明授权
    Information processing apparatus, information processing method, and program 有权
    信息处理装置,信息处理方法和程序

    公开(公告)号:US08996440B2

    公开(公告)日:2015-03-31

    申请号:US13474159

    申请日:2012-05-17

    IPC分类号: G06N5/02 G06Q10/10

    CPC分类号: G06Q10/109

    摘要: An information processing apparatus configured to create a schedule to be presented to a user includes an estimation unit and a creation unit. The estimation unit is configured to estimate whether or not the user acts in accordance with a first schedule including a task to do for accomplishing a preset aim. The creation unit is configured to create, when estimated that the user does not act in accordance with the first schedule, a new second schedule for accomplishing the aim from a state of the user who acts without following the first schedule.

    摘要翻译: 被配置为创建要呈现给用户的日程表的信息处理设备包括估计单元和创建单元。 估计单元被配置为估计用户是否根据包括要完成预设目标的任务的第一调度进行动作。 创建单元被配置为当估计用户不按照第一时间表行动时创建新的第二计划,用于从不遵循第一进度的行为的用户的状态完成目标。

    Wavelength selective switch
    5.
    发明授权
    Wavelength selective switch 有权
    波长选择开关

    公开(公告)号:US08761554B2

    公开(公告)日:2014-06-24

    申请号:US13419646

    申请日:2012-03-14

    IPC分类号: G02B6/26 G02B6/42

    CPC分类号: G02B6/3518 G02B6/3534

    摘要: Provided is a wavelength selective switch, which includes: an input/output unit; a dispersive portion; a condensing optical system; and the deflection portion. The input/output unit has input/output ports. The dispersive portion disperses signal light incident from the input/output ports. The condensing optical system condenses a plurality of signal light beams dispersed by the dispersive portion. The deflection portion has a plurality of deflection elements. The deflection elements deflect, along a second direction, the signal light beams condensed by the condensing optical system. In the condensing optical system, the aberration amount of the meridional component in a sagittal coma aberration remains substantially constant irrespective of an angle formed between the optical axis of the condensing optical system and a signal light beam incident on the condensing optical system from the input/output portion, at an incident position of the incident signal light beam at a certain height in the second direction.

    摘要翻译: 提供一种波长选择开关,其包括:输入/输出单元; 分散部分; 聚光光学系统; 和偏转部。 输入/输出单元具有输入/输出端口。 色散部分分散从输入/输出端口入射的信号光。 聚光光学系统凝聚由分散部分散射的多个信号光束。 偏转部分具有多个偏转元件。 偏转元件沿着第二方向偏转由聚光光学系统会聚的信号光束。 在聚光光学系统中,与聚光光学系统的光轴和入射到聚光光学系统的信号光束之间的角度不同,矢状彗差中的子午分量的像差量保持基本恒定, 在入射信号光束的入射位置处,在第二方向上处于一定高度。

    INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM
    6.
    发明申请
    INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM 有权
    信息处理设备,信息处理方法和程序

    公开(公告)号:US20120310873A1

    公开(公告)日:2012-12-06

    申请号:US13474159

    申请日:2012-05-17

    IPC分类号: G06N5/02

    CPC分类号: G06Q10/109

    摘要: An information processing apparatus configured to create a schedule to be presented to a user includes an estimation unit and a creation unit. The estimation unit is configured to estimate whether or not the user acts in accordance with a first schedule including a task to do for accomplishing a preset aim. The creation unit is configured to create, when estimated that the user does not act in accordance with the first schedule, a new second schedule for accomplishing the aim from a state of the user who acts without following the first schedule.

    摘要翻译: 被配置为创建要呈现给用户的日程表的信息处理设备包括估计单元和创建单元。 估计单元被配置为估计用户是否根据包括要完成预设目标的任务的第一调度进行动作。 创建单元被配置为当估计用户不按照第一时间表行动时创建新的第二计划,用于从不遵循第一进度的行为的用户的状态完成目标。

    EBULLIENT COOLING DEVICE
    7.
    发明申请
    EBULLIENT COOLING DEVICE 审中-公开
    EBULLI冷却装置

    公开(公告)号:US20120111550A1

    公开(公告)日:2012-05-10

    申请号:US13254680

    申请日:2010-03-09

    IPC分类号: F28F1/10

    摘要: An ebullient cooling device having a simple structure and capable of limiting the bubbles to an appropriate volume. The ebullient cooling device for cooling a heat generating element is provided with a plurality of vertically arranged cooling channels comprising a lower channel (2), a middle channel (3) and un upper channel (4). Each cooling channel has cooling fins (12) for guiding a refrigerant to flow in a vertical direction, and a vapor discharge path (16) formed at the side of the cooling fins (12) that is opposite the side in contact with the heat generating element. Furthermore, flow path partition/vapor discharge guiding plates (18) are provided between the cooling channels so that the bubbles that have been generated are guided to the vapor discharge path (16) and prevented from moving into the subsequent cooling channel.

    摘要翻译: 一种沸腾冷却装置,具有简单的结构并且能够将气泡限制到适当的体积。 用于冷却发热元件的沸腾冷却装置设置有多个垂直布置的冷却通道,其包括下通道(2),中间通道(3)和非上通道(4)。 每个冷却通道具有用于引导制冷剂沿垂直方向流动的冷却片(12)和形成在与发热量接触的一侧相反的散热片(12)侧的蒸汽排出通道(16) 元件。 此外,在冷却通道之间设置有流路分隔/蒸汽排出引导板(18),使得已经产生的气泡被引导到蒸气排放路径(16)并阻止其进入随后的冷却通道。

    Integrated circuit chip with modular design
    8.
    发明授权
    Integrated circuit chip with modular design 失效
    集成电路芯片采用模块化设计

    公开(公告)号:US08032849B2

    公开(公告)日:2011-10-04

    申请号:US12130268

    申请日:2008-05-30

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5045

    摘要: Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.

    摘要翻译: 公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。 该方法包括保持每个模块的尺寸基本相同,并使总线,电源,时钟和I / O连接在所有模块上配置相同。 对易用性的进一步要求是尽可能地推广每个模块的能力,并将诸如测试之类的功能分散在每个模块内主要执行。 这种考虑或规则的使用大大简化了给定类型的定制芯片的设计,并且基于初始的芯片设计极大地促进了其他定制芯片的设计,其应用类似,但是在初始芯片的成功完成之后。 给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间,以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。 任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

    System and method for data synchronization for a computer architecture for broadband networks
    9.
    发明授权
    System and method for data synchronization for a computer architecture for broadband networks 有权
    宽带网络计算机架构的数据同步系统和方法

    公开(公告)号:US08028288B2

    公开(公告)日:2011-09-27

    申请号:US10967433

    申请日:2004-10-18

    IPC分类号: G06F9/46

    CPC分类号: G06F12/1466 H04L69/12

    摘要: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.

    摘要翻译: 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构,通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器,多个处理单元,处理单元处理程序的多个本地存储器,直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 还提供了一种用于处理计算机任务的处理系统。 第一处理器是第一处理器类型,并且多个第二处理器是第二处理器类型。 第二处理器之一通过向第一和第二处理器中的至少一个提供任务来管理计算任务的进程调度。