公开(公告)号：US20110279150A1

公开(公告)日：2011-11-17

申请号：US12889492

申请日：2010-09-24

申请人： Yung-Chow PENG ,  Wen-Shen CHOU ,  Ching-Ho CHANG ,  Wan-Te CHEN

发明人： Yung-Chow PENG ,  Wen-Shen CHOU ,  Ching-Ho CHANG ,  Wan-Te CHEN

IPC分类号： H03K3/00

CPC分类号： G09G3/3688 ,  G09G2310/027

摘要： A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.

摘要翻译： 驱动器利用运算放大器的端子的选择性偏置来减小运算放大器输出中的偏移。 每个运算放大器输入包括包括NMOS晶体管和PMOS晶体管的差分输入对晶体管。 在输入电压范围的低端和高端，这些晶体管选择性地和单独地耦合到标准输入或偏置为导通，以便补偿偏移补偿。 晶体管以常规方式偏置，用于在电压范围的低端和高端之间的输入电压。

公开(公告)号：US20140042585A1

公开(公告)日：2014-02-13

申请号：US13569717

申请日：2012-08-08

申请人： Yung-Chow PENG ,  Wen-Shen CHOU ,  Jaw-Juinn HORNG

发明人： Yung-Chow PENG ,  Wen-Shen CHOU ,  Jaw-Juinn HORNG

IPC分类号： G06F17/50 ,  H01L27/00

CPC分类号： H01L27/0207 ,  G06F17/5072 ,  G06F17/5081

摘要： This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.

摘要翻译： 本公开涉及制造半导体器件的方法。 该方法包括将半导体器件的示意图设计与半导体器件的布局设计进行比较。 该方法还包括基于布局设计生成布局样式信息，并基于布局设计和原理图设计生成阵列边缘信息。 该方法还包括使用布局样式信息和阵列边缘信息来选择性地修改使用智能虚拟插入的布局设计。 该方法还包括使用布局样式信息和阵列边缘信息对修改的布局设计执行设计规则检查。 本公开还涉及一种用于制造半导体器件和半导体器件的系统。

公开(公告)号：US20130195142A1

公开(公告)日：2013-08-01

申请号：US13428549

申请日：2012-03-23

申请人： Yung-Chow PENG ,  Ching-Ho CHANG ,  Jui-Cheng HUANG

发明人： Yung-Chow PENG ,  Ching-Ho CHANG ,  Jui-Cheng HUANG

IPC分类号： G01K7/01 ,  G01K7/00 ,  H02B1/00

CPC分类号： G01K7/01 ,  Y10T307/76

摘要： A thermal sensing system includes a circuit having a layout including standard cells arranged in rows and columns. First and second current sources provide first and second currents, respectively. The thermal sensing system includes thermal sensing units, first and second switching modules, and an analog to digital converter (ADC). Each thermal sensing unit is configured to provide a voltage drop dependent on a temperature at that thermal sensing unit. The first switching module is configured to select one of the thermal sensing units. The second switching module includes at least one switch controllable by a control signal. The at least one switch is configured to selectively couple the thermal sensing units, based on the control signal, to one of the first and second current sources, via the first switching module. The ADC is configured to convert an analog voltage, provided by the selected thermal sensing unit, to a digital value.

摘要翻译： 热感测系统包括具有布置成行和列的标准单元的布局的电路。 第一和第二电流源分别提供第一和第二电流。 热感测系统包括热敏单元，第一和第二开关模块以及模数转换器（ADC）。 每个热敏单元被配置成提供取决于该热感测单元处的温度的电压降。 第一开关模块被配置为选择一个热感测单元。 第二开关模块包括可由控制信号控制的至少一个开关。 所述至少一个开关被配置为经由所述第一开关模块将所述热感测单元基于所述控制信号选择性地耦合到所述第一和第二电流源之一。 ADC配置为将所选热敏单元提供的模拟电压转换为数字值。

公开(公告)号：US20120176193A1

公开(公告)日：2012-07-12

申请号：US12987464

申请日：2011-01-10

申请人： Renjeng CHIANG ,  Yung-Chow PENG

发明人： Renjeng CHIANG ,  Yung-Chow PENG

IPC分类号： H01L25/00 ,  H01L21/98

CPC分类号： H01L27/0207 ,  H01L23/4824 ,  H01L23/5286 ,  H01L23/5329 ,  H01L24/05 ,  H01L27/092 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2924/01068 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00

摘要： A driver for a semiconductor chip, the driver having a drain wire with a first end and a second end and p and n-type transistors each with a source, gate and drain. The source of the p-type transistors connected to a positive power supply line, the source of the n-type transistors connected to a ground power supply line. The gates of the p and n-type transistors connected to a first and second input signals respectively. The drains of the p and n-type transistors connected to the drain wire. The p and n-type transistors arranged so that a difference between a number of n-type transistors connected to the drain wire and a number of p-type transistors connected to the drain wire between the first end of the drain wire and all distances along the drain wire being less than two.

摘要翻译： 一种用于半导体芯片的驱动器，该驱动器具有带有第一端和第二端的漏极线以及分别具有源极，栅极和漏极的p型和n型晶体管。 连接到正电源线的p型晶体管的源极，连接到地电源线的n型晶体管的源极。 分别连接到第一和第二输入信号的p型和n型晶体管的栅极。 连接到漏极线的p型和n型晶体管的漏极。 p型和n型晶体管被布置成使得连接到漏极线的n个晶体管的数量与在漏极线的第一端之间连接到漏极线的多个p型晶体管之间的差异以及沿着 漏极线小于2。

公开(公告)号：US20110090947A1

公开(公告)日：2011-04-21

申请号：US12836999

申请日：2010-07-15

申请人： Yung-Chow PENG ,  Yu-Chun LIN

发明人： Yung-Chow PENG ,  Yu-Chun LIN

IPC分类号： H04L27/01

CPC分类号： H04L25/03885 ,  H04L25/03006 ,  H04L25/03057 ,  H04L2025/03535 ,  H04L2025/03681 ,  H04L2025/03707 ,  H04L2025/03745

摘要： A method for updating a tap coefficient of a decision feedback equalizer is provided. The method includes sampling a first input signal received by a sampler of a decision feedback equalizer. It is determined if an amplitude of the first input signal falls within a range defined between a first predetermined voltage level and a second predetermined voltage level. If the amplitude of the first input signal falls outside the range, a tap coefficient is updated to generate an updated tap coefficient that is fed back to adjust an amplitude of a second input signal received at an input end of the decision feedback equalizer. If the amplitude of the first input signal falls within the range, the tap coefficient is free from being updated.

摘要翻译： 提供了一种用于更新判决反馈均衡器的抽头系数的方法。 该方法包括对由判决反馈均衡器的采样器接收的第一输入信号进行采样。 确定第一输入信号的振幅是否落在在第一预定电压电平和第二预定电压电平之间限定的范围内。 如果第一输入信号的振幅超出该范围，则抽头系数被更新以产生被反馈的更新抽头系数，以调整在判决反馈均衡器的输入端接收的第二输入信号的幅度。 如果第一输入信号的振幅落在该范围内，则抽头系数不被更新。

公开(公告)号：US20140007031A1

公开(公告)日：2014-01-02

申请号：US13539258

申请日：2012-06-29

申请人： Mu-Jen HUANG ,  Chih Chi HSIAO ,  Wei-Ting LIN ,  Tsung-Hsin YU ,  Chien-Wen CHEN ,  Yung-Chow PENG

发明人： Mu-Jen HUANG ,  Chih Chi HSIAO ,  Wei-Ting LIN ,  Tsung-Hsin YU ,  Chien-Wen CHEN ,  Yung-Chow PENG

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

摘要翻译： 在由至少一个处理器执行的半导体器件设计方法中，所述至少一个处理器提取半导体器件的布局中的至少一个电气部件的位置数据。 由至少一个处理器提取与所述至少一个电气部件相关联并且基于所述半导体器件的操作的模拟的电压数据。 基于所提取的位置数据，所提取的电压数据由所述至少一个处理器并入所述布局中以生成所述半导体器件的修改的布局。

公开(公告)号：US20130147057A1

公开(公告)日：2013-06-13

申请号：US13324405

申请日：2011-12-13

申请人： Jaw-Juinn HORNG ,  Chia-Lin YU ,  Chung-Hui CHEN ,  Der-Chyang YEH ,  Yung-Chow PENG

发明人： Jaw-Juinn HORNG ,  Chia-Lin YU ,  Chung-Hui CHEN ,  Der-Chyang YEH ,  Yung-Chow PENG

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

摘要翻译： 提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。 隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。 周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

公开(公告)号：US20120126897A1

公开(公告)日：2012-05-24

申请号：US13364043

申请日：2012-02-01

申请人： Yu-Wei LIN ,  Yung-Chow PENG

发明人： Yu-Wei LIN ,  Yung-Chow PENG

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45475 ,  H03F3/45632 ,  H03F3/45928 ,  H03F2203/45512 ,  H03F2203/45588

摘要： A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.

摘要翻译： 电路提供对应于差分输入Inn和Inp的第一电流，以及对应于共模输入Vcm的第二电流。 电路然后将差分电流和共模电流反射到第三电流和第四电流。 基于镜像差分电流和镜像共模电流之间的差异，电路拉起或拉下这些电流，以平衡差分输入和共模输入之间的相应差值。 实际上，该电路将输入共模电压调整到期望的电平，而不给它提供上升到不需要的电平的机会。

公开(公告)号：US20130185689A1

公开(公告)日：2013-07-18

申请号：US13352738

申请日：2012-01-18

申请人： Chien-Hung CHEN ,  Yung-Chow PENG ,  Chung-Hui CHEN ,  Chih Ming YANG

发明人： Chien-Hung CHEN ,  Yung-Chow PENG ,  Chung-Hui CHEN ,  Chih Ming YANG

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/12 ,  H01L27/0207 ,  H01L29/94

摘要： A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components.

摘要翻译： 根据一组设计规则生成半导体部件的优化布局的方法包括为包括一个或多个半导体部件的单元单元生成多个配置，每个配置满足设计规则的一些但不是全部 。 对于每个配置，检查作为单位单元的重复图案的布局是否满足剩余的设计规则。 在满足所有设计规则的配置中，选择提供最佳的属性值的配置用于生成半导体部件的优化布局。

公开(公告)号：US20110260746A1

公开(公告)日：2011-10-27

申请号：US12764346

申请日：2010-04-21

申请人： Jui-Cheng HUANG ,  Yung-Chow PENG ,  Ruey-Bin SHEEN

发明人： Jui-Cheng HUANG ,  Yung-Chow PENG ,  Ruey-Bin SHEEN

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G09G3/3685 ,  G09G3/006 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2330/12

摘要： A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver includes at least one digital-to-analog converter (DAC) and at least one buffer coupled to the respective DAC, wherein the buffer is reconfigurable as a comparator. A first input signal and a second input signal are coupled to the comparator. The first input signal is a predetermined reference voltage level. The second input signal is a test offset voltage in a test range.

摘要翻译： 用于液晶显示器（LCD）源驱动器的内置自检（BIST）电路包括至少一个数模转换器（DAC）和耦合到相应DAC的至少一个缓冲器，其中缓冲器可重新配置 作为比较。 第一输入信号和第二输入信号耦合到比较器。 第一输入信号是预定的参考电压电平。 第二输入信号是测试范围内的测试偏移电压。