公开(公告)号：US11705437B1

公开(公告)日：2023-07-18

申请号：US18098726

申请日：2023-01-19

Applicant: ZHEJIANG LAB

Inventor： Qingwen Deng ,  Kun Zhang ,  Shunbin Li ,  Ruyun Zhang

IPC: H01L25/065 ,  H01L21/67 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/67103 ,  H01L23/481

Abstract: An interconnection structure of a system on wafer and a PCB based on a TSV process and a method for manufacturing the same. The structure comprises a bottom structural part and a top structural part, the upper surface of the bottom structural part is provided with a plurality of positioning holes; the lower surface of the top structural part is provided with positioning pins; the upper surface of the bottom structural part is provided with a bottom groove, and a system on wafer is arranged in the bottom groove; the lower surface of the system on wafer is connected with the bottom groove; the lower surface of the top structural part is provided with a top groove, and a PCB preformed die is connected in the top groove, and the other end of the PCB preformed die is connected with the system on wafer by an elastic connector.

公开(公告)号：US11887964B1

公开(公告)日：2024-01-30

申请号：US18298379

申请日：2023-04-11

Applicant: ZHEJIANG LAB

Inventor： Shunbin Li ,  Weihao Wang ,  Ruyun Zhang ,  Qinrang Liu ,  Zhiquan Wan ,  Jianliang Shen

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/306

CPC classification number: H01L25/0655 ,  H01L21/30625 ,  H01L21/486 ,  H01L21/565 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/182

Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.

公开(公告)号：US11876071B1

公开(公告)日：2024-01-16

申请号：US18328797

申请日：2023-06-05

Applicant: ZHEJIANG LAB

Inventor： Weihao Wang ,  Shunbin Li ,  Guandong Liu ,  Ruyun Zhang ,  Qinrang Liu ,  Zhiquan Wan ,  Jianliang Shen

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/81 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/11462 ,  H01L2224/1403 ,  H01L2224/145 ,  H01L2224/14131

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

公开(公告)号：US11860893B1

公开(公告)日：2024-01-02

申请号：US17981368

申请日：2022-11-04

Applicant: ZHEJIANG LAB

Inventor： Peilei Wang ,  Ruyun Zhang ,  Tao Zou ,  Shunbin Li ,  Peilong Huang

IPC: G06F16/20 ,  G06F16/27 ,  G06F16/25 ,  G06F9/54 ,  H04L67/56

CPC classification number: G06F16/27 ,  G06F9/54 ,  G06F16/256 ,  H04L67/56

Abstract: Disclosed are an input/output proxy method and apparatus for a mimic Redis database. Through a pseudo server module, it is ensured that the interface of the Redis database is consistent with the external interface of the native Redis, so that it is convenient to implant the Redis database into arbitrary Redis application scenarios; the isolation of the modules inside is realized by independent processes, thus facilitating independent development, maintenance and expansion; and the synchronization function is integrated into the input/output proxy to achieve resource reuse; for the synchronization function, the random credit attenuation mechanism is cleverly utilized to ensure the synchronization function while taking into account the saving of resources.

公开(公告)号：US12177072B1

公开(公告)日：2024-12-24

申请号：US18555805

申请日：2023-07-13

Applicant: ZHEJIANG LAB

Inventor： Peilei Wang ,  Ruyun Zhang ,  Jun Zhu ,  Tao Zou ,  Shunbin Li ,  Qi Xu

IPC: H04L41/082 ,  H04L41/0894 ,  H04L67/1097

Abstract: A data storage system includes: a server, a client and a control end; the control end is configured to generate a configuration file, and send the configuration file to the client and the server; the client is configured to generate an encapsulation rule based on the configuration file, generate a storage request, perform encapsulation on the storage request to obtain a message packet, and send the message packet to the server; the server is configured to generate an extraction unit and an action unit based on the configuration file, analyze the message packet to obtain the target information, write the target information into each extraction unit, read action information and determine an action unit matching the action information as a target action unit, and execute the storage actions corresponding to the target action unit to store byte stream data of the target information.

公开(公告)号：US12149642B2

公开(公告)日：2024-11-19

申请号：US17876553

申请日：2022-07-29

Applicant: Zhejiang Lab

Inventor： Hanguang Luo ,  Tao Zou ,  Shunbin Li ,  Qi Xu ,  Huifeng Zhang

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08

Abstract: The present disclosure belongs to an identity authentication technology in network security field, and relates to a lightweight identity authentication method. The method utilizes lightweight operations of the physical unclonable function, Hash operation, XOR operation, etc. for bidirectional authentication between an authentication server and an Internet of Things resource-limited device, and particularly utilizes uniqueness of an integrated circuit (IC) physical microstructure created by the physical unclonable function in the resource-limited device in a manufacturing process to design an engineering-implementable information desynchronization recovery mechanism of two authentication parties by optimizing an interaction mode of input challenge and output response of the physical unclonable function, thereby solving the problem that the same lightweight identity authentication type solution cannot ensure forward security and resist desynchronization attack, further reducing resource cost for an identity authentication process, and effectively improving security and operation efficiency of identity authentication of the Internet of Things resource-limited device.

公开(公告)号：US12095862B1

公开(公告)日：2024-09-17

申请号：US18565436

申请日：2023-07-05

Applicant: ZHEJIANG LAB

Inventor： Peilei Wang ,  Ruyun Zhang ,  Tao Zou ,  Shunbin Li ,  Peilong Huang

IPC: H04L67/1097 ,  G06F9/54

CPC classification number: H04L67/1097 ,  G06F9/54

Abstract: The present disclosure provides a data processing system and a data processing method. The system includes: a client interaction module, a subscribing and publishing module, a storage module, and a sub-database management module. The client interaction module is configured to: receive an interaction request sent by a client, analyze the interaction request to obtain an analyzing result, and based on the analyzing result, determine a process type to be started and start a response process of the process type, and repackage the interaction request and send the repackaged interaction request to the response process, where the process type includes a first process type corresponding to the subscribing and publishing module, a second process type corresponding to the storage module and a third process type corresponding to the sub-database management module.

公开(公告)号：US12112115B2

公开(公告)日：2024-10-08

申请号：US18328800

申请日：2023-06-05

Applicant: ZHEJIANG LAB

Inventor： Shunbin Li ,  Weihao Wang ,  Ruyun Zhang ,  Qinrang Liu ,  Zhiquan Wan ,  Jianliang Shen

IPC: G06F30/396 ,  G06F115/02 ,  G06F119/22 ,  H01L27/02

CPC classification number: G06F30/396 ,  H01L27/0207 ,  G06F2115/02 ,  G06F2119/22

Abstract: A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.

公开(公告)号：US11983481B2

公开(公告)日：2024-05-14

申请号：US18351464

申请日：2023-07-12

Applicant: ZHEJIANG LAB

Inventor： Zhiquan Wan ,  Shunbin Li ,  Ruyun Zhang ,  Weihao Wang ,  Qingwen Deng

IPC: G06F30/398 ,  G06F30/392 ,  G06F117/12

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2117/12

Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

公开(公告)号：US11776879B1

公开(公告)日：2023-10-03

申请号：US18306948

申请日：2023-04-25

Applicant: ZHEJIANG LAB

Inventor： Guandong Liu ,  Weihao Wang ,  Shunbin Li ,  Ruyun Zhang

IPC: H01L23/02 ,  H01L23/473 ,  H01L23/498 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/473 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/32245 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/182

Abstract: The present disclosure discloses a three-dimensional stacked package structure with a micro-channel heat dissipation structure and a packaging method thereof. The three-dimensional stacked package structure includes a chip package portion comprising a multi-layered structure with stacked chips, wherein the stacked chips are provided with through silicon vias and packaged in a three-dimensional stacked packaging manner and a silicon substrate package portion comprising a silicon substrate. The silicon substrate is provided with micro bumps which are to be interconnected with external lead wires. The chip package portion is assembled on the silicon substrate by bonding with the micro bumps. The stacked chips are etched with micro-channels and through holes corresponding to each other. The micro-channels are for coolant flowing in a horizontal direction, and the through holes are for coolant flowing in upper and lower layers. Sealing rings are arranged around the micro-channels and the through holes.