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    Integrated structure for reduced leakage and improved fill-factor in CMOS pixel
    2.
    发明授权
    Integrated structure for reduced leakage and improved fill-factor in CMOS pixel 有权
    集成结构，可减少泄漏，改善CMOS像素的填充因子

    公开(公告)号：US06392263B1

    公开(公告)日：2002-05-21

    申请号：US09855251

    申请日：2001-05-15

    申请人： Zhiliang J. Chen ,  Kuok Y. Ling ,  Hisashi Shichijo ,  Katsuo Komatsuzaki ,  Chin-Yu Tsai

    发明人： Zhiliang J. Chen ,  Kuok Y. Ling ,  Hisashi Shichijo ,  Katsuo Komatsuzaki ,  Chin-Yu Tsai

    IPC分类号： H01L2972

    CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L27/1463

    摘要： A densely integrated pixel, fabricated by CMOS technology, comprises a photodiode formed by a n-well, with cathode, surrounded by a p-well; a reset MOS transistor formed such that its polysilicon gate is positioned, for diode control, across the junction formed by p-well and n-well regions, and its source is merged with the photodiode cathode; and a sensing MOS transistor formed such that its source is combined with the drain of the reset transistor and its gate is electrically connected to the source of the reset transistor. In the pixel of the invention, the photodiode leakage current is greatly reduced, because no n+/p-well junction is connected to the photodiode, and the fill factor is improved, because the pixel size is much reduced.

    摘要翻译： 由CMOS技术制造的密集集成的像素包括由n阱形成的光电二极管，阴极由p阱包围; 复位MOS晶体管形成为使得其多晶硅栅极被定位用于二极管控制，跨越由p阱和n阱区域形成的结，并且其源极与光电二极管阴极合并; 以及形成为使得其源极与复位晶体管的漏极组合的感测MOS晶体管，并且其栅极电连接到复位晶体管的源极。在本发明的像素中，光电二极管的漏电流大大降低，因为没有 n + / p-阱结连接到光电二极管，并且填充因子得到改善，因为像素尺寸大大降低。

    CMOS photodiode having reduced dark current and improved light sensitivity and responsivity
    4.
    发明授权
    CMOS photodiode having reduced dark current and improved light sensitivity and responsivity 有权
    CMOS光电二极管具有降低的暗电流和改善的光敏度和响应性

    公开(公告)号：US06753202B2

    公开(公告)日：2004-06-22

    申请号：US10446910

    申请日：2003-05-28

    申请人： Zhiliang J. Chen ,  Kuok Y. Ling ,  Hisashi Shichijo ,  Katsuo Komatsuzaki ,  Chin-Yu Tsai

    发明人： Zhiliang J. Chen ,  Kuok Y. Ling ,  Hisashi Shichijo ,  Katsuo Komatsuzaki ,  Chin-Yu Tsai

    IPC分类号： H01L2100

    CPC分类号： H01L31/1126 ,  H01L27/14643 ,  H01L27/148

    摘要： A method for the fabrication of a light-sensing diode in a high-resistivity semiconductor substrate. A high-energy implant of ions into the substrate is patterned to form an annular well of the same conductivity type as the substrate; followed by a second high-energy implant of the opposite conductivity type, within the center of the annulus; followed by a third implant, of lower energy and high dosage, to form a region of the first conductivity type extending laterally near the substrate surface. The resulting diode junction is thereby patterned to include two planes near the substrate surface, allowing incident light to traverse the junction twice.

    摘要翻译： 一种在高电阻率半导体衬底中制造感光二极管的方法。 将高能量离子注入到衬底中被图案化以形成与衬底相同的导电类型的环形阱; 之后是相对导电类型的第二高能量植入在环的中心内; 随后是较低能量和高剂量的第三种植入物，以形成在衬底表面附近横向延伸的第一导电类型的区域。 由此形成的二极管结被图案化以包括靠近衬底表面的两个平面，允许入射光穿过接合两次。

    Shared data buffer in FeRAM utilizing word line direction segmentation
    5.
    发明授权
    Shared data buffer in FeRAM utilizing word line direction segmentation 有权
    FeRAM中的共享数据缓冲区利用字线方向分割

    公开(公告)号：US06873536B2

    公开(公告)日：2005-03-29

    申请号：US10126394

    申请日：2002-04-19

    申请人： Katsuo Komatsuzaki

    发明人： Katsuo Komatsuzaki

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a data buffer, and a sense amplifier between several segments of an array of FeRAM memory cells associated with a plurality of plate lines and/or word lines of the array. Various combinations of segmented bit lines, segmented plate lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.

    摘要翻译： 描述了一种用于访问和感测具有开放位线架构的FeRAM存储器阵列的存储单元的铁电存储器件系统和方法。 存储器件允许在与阵列的多个板条线和/或字线相关联的FeRAM存储器单元阵列的几个段之间共享某些存储器电路，例如数据缓冲器和读出放大器。 分段位线，分段板线和/或分段字线的各种组合便于在阵列段或多个存储单元阵列之间共享设备的存储器电路。

    Shared sense amplifier for ferro-electric memory cell
    6.
    发明授权
    Shared sense amplifier for ferro-electric memory cell 有权
    用于铁电存储单元的共享读出放大器

    公开(公告)号：US06574135B1

    公开(公告)日：2003-06-03

    申请号：US10126844

    申请日：2002-04-19

    申请人： Katsuo Komatsuzaki

    发明人： Katsuo Komatsuzaki

    IPC分类号： G11C1122

    CPC分类号： G11C11/22 ,  G11C7/06 ,  G11C7/18 ,  G11C2211/4013

    摘要： A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a sense amplifier, a data buffer, and a dummy cell between several segments of an array of FeRAM memory cells associated with a pair of bitlines of the array. Various combinations of segmented bit lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.

    摘要翻译： 描述了一种用于访问和感测具有开放位线架构的FeRAM存储器阵列的存储单元的铁电存储器件系统和方法。 存储器件允许在与阵列的一对位线相关联的FeRAM存储器单元阵列的几个段之间共享某些存储器电路，例如读出放大器，数据缓冲器和虚拟单元。 分段位线和/或分段字线的各种组合便于在阵列段或多个存储单元阵列之间共享器件的存储器电路。

    Semiconductor device fabrication process
    7.
    发明授权
    Semiconductor device fabrication process 失效
    半导体器件制造工艺

    公开(公告)号：US4708768A

    公开(公告)日：1987-11-24

    申请号：US24238

    申请日：1987-03-10

    申请人： Osaomi Enomoto ,  Katsuo Komatsuzaki

    发明人： Osaomi Enomoto ,  Katsuo Komatsuzaki

    IPC分类号： H01L21/76 ,  C23C16/04 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

    CPC分类号： H01L21/76216 ,  C23C16/042 ,  H01L21/32

    摘要： A semiconductor device fabrication process comprising the following sequential steps:Sequential formation of an oxide layer and first layer of masking material resistant both to oxidation (particularly preventing the action of oxidants, such as water vapors and O.sub.2) and heat, on a principal plane of semiconductor substrate;Patternwise removal of these two layers in overlapping positions to form wells with the above semiconductor substrate exposed at bottom;Selective removal of the above oxide layer only around the wells thus formed to leave recesses;Deposition of the second layer of masking material resistant both oxidation and heat on the exposed surfaces of semiconductor substrate at the bottom of the above wells and in the recesses that are left after the above selective removal of oxide layer;Removal of the above second layer of masking material from the bottom of wells with the masking material left in the above recesses; andSelective oxidation of exposed surfaces of above semiconductor substrate under masking with the first and second layers of masking material that remain.

    摘要翻译： 一种半导体器件制造方法，包括以下顺序步骤：顺序形成氧化物层和掩蔽材料的第一层，其能够抵抗氧化（特别是防止氧化剂如水蒸汽和氧气的作用）和热，在主平面上 半导体衬底; 在重叠位置上以图形方式去除这两层以形成具有暴露在底部的上述半导体衬底的阱; 选择性地去除上述氧化物层，仅在由此形成的孔留下凹槽; 在上述孔的底部和在上述选择性去除氧化物层之后留下的凹槽中，在半导体衬底的暴露表面上沉积第二层掩模材料，以抵抗氧化和加热; 从孔的底部去除上述第二层掩模材料，其中掩蔽材料留在上述凹槽中; 以及在保留的第一和第二掩蔽材料层掩蔽下的上述半导体衬底的暴露表面的选择性氧化。

    Apparatus and methods for imprint reduction for ferroelectric memory cell
    8.
    发明授权
    Apparatus and methods for imprint reduction for ferroelectric memory cell 有权
    铁电存储器单元压印减少的装置和方法

    公开(公告)号：US06590798B1

    公开(公告)日：2003-07-08

    申请号：US10141017

    申请日：2002-05-08

    申请人： Katsuo Komatsuzaki

    发明人： Katsuo Komatsuzaki

    IPC分类号： G11C1122

    CPC分类号： G11C11/22

    摘要： Memory devices and methods are disclosed for reading a restoring data from and to ferroelectric memory cells, wherein a data bit is sensed from a data memory cell, a toggle bit is sensed from a toggle memory cell, and the sensed data bit is transferred to an IO line in either inverted form or non-inverted form according to the sensed toggle bit. The sensed data bit and the toggle bit are then inverted and restored to the data and toggle memory cells so as to mitigate or reduce cell imprint.

    摘要翻译： 公开了用于从强电介质存储单元读取恢复数据的存储器件和方法，其中从数据存储单元检测数据位，从触发存储器单元感测到触发位，并将所感测的数据位传送到 IO线根据感测的切换位以倒置形式或非倒置形式。 然后将检测到的数据位和触发位反转并恢复到数据和触发存储器单元，以减轻或减少单元印记。

    Matched delay word line strap
    9.
    发明授权
    Matched delay word line strap 失效
    匹配延迟字线条

    公开(公告)号：US5841688A

    公开(公告)日：1998-11-24

    申请号：US883738

    申请日：1997-06-27

    申请人： Shunichi Sukegawa ,  Hugh P. McAdams ,  Tadashi Tachibana ,  Katsuo Komatsuzaki ,  Takeshi Sakai

    发明人： Shunichi Sukegawa ,  Hugh P. McAdams ,  Tadashi Tachibana ,  Katsuo Komatsuzaki ,  Takeshi Sakai

    IPC分类号： G11C5/06 ,  G11C8/14 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/00

    CPC分类号： H01L27/10891 ,  G11C11/408 ,  G11C5/063 ,  G11C8/14 ,  H01L27/10897

    摘要： A circuit is designed with a first lower conductor (500) having two ends. One end of the first lower conductor is coupled to a first signal source (386). A first upper conductor (544) has two ends and is spaced apart from the first lower conductor by a distance less than an allowable spacing between adjacent lower conductors. One end of the first upper conductor is coupled to a second signal source (384). A second upper conductor (508) has two ends. One end of the second upper conductor is coupled to another end of the first lower conductor for receiving a signal from the first signal source. A second lower conductor (552) has two ends and is spaced apart from the second upper conductor by a distance less than the allowable spacing between adjacent lower conductors. One end of the second lower conductor is coupled to another end of the first upper conductor for receiving a signal from the second signal source. Since the upper and lower conductors are spaced apart by a distance less than an allowable spacing between adjacent lower conductors, layout area is conserved. Total resistance of conductors connected to each signal source is the same, so signal delay is the same.

    摘要翻译： 电路设计有具有两端的第一下导体（500）。 第一下导体的一端耦合到第一信号源（386）。 第一上导体（544）具有两个端部，并且与第一下导体间隔一个小于相邻下导体之间允许间隔的距离。 第一上导体的一端耦合到第二信号源（384）。 第二上导体（508）具有两端。 第二上导体的一端耦合到第一下导体的另一端，用于接收来自第一信号源的信号。 第二下导体（552）具有两个端部，并且与第二上导体间隔一个小于相邻下导体之间允许间隔的距离。 第二下导体的一端耦合到第一上导体的另一端，用于从第二信号源接收信号。 由于上导体和下导体间隔距离小于相邻下导体之间的允许间距，所以布局面积是保守的。 连接到每个信号源的导体的总电阻是相同的，因此信号延迟是相同的。

    Series feram cell array
    10.
    发明申请
    Series feram cell array 有权
    系列火炬单元阵列

    公开(公告)号：US20050146916A1

    公开(公告)日：2005-07-07

    申请号：US11048255

    申请日：2005-01-31

    申请人： Katsuo Komatsuzaki

    发明人： Katsuo Komatsuzaki

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.

    摘要翻译： 公开了存储器件和存储器单元组，其包括使用单个位线可访问的串联连接的铁电（FE）存储器单元。 电池单独地包括晶体管和FE电容器，其中组或阵列中的单个单元被连接到位线，以在读取，写入和/或恢复操作期间进行外部访问。 还公开了用于读取存储器单元组中的靶细胞的方法。