公开(公告)号：US08629006B2

公开(公告)日：2014-01-14

申请号：US11634039

申请日：2006-12-05

申请人： Steven Winegarden ,  Ronald Nicholson ,  John Jun Yu

发明人： Steven Winegarden ,  Ronald Nicholson ,  John Jun Yu

IPC分类号： H01L21/82

CPC分类号： H01L27/11807 ,  H01L27/0207

摘要： The present invention provides architectures for hybrid integrated circuits and methods for producing these hybrid integrated circuits that contain both field programmable gate arrays and mask programmable gate arrays, a form of application specific integrated circuits. Methods for producing an integrated circuit that is field programmable as well as mask programmable include the steps of: designing wafer bank layers and finishing layers, where the wafer bank layers provide a plurality of selectable functional blocks; fabricating said wafer bank layers; designing mask programmed interconnect layers for said integrated circuit, where the interconnect layers interconnect selected ones of the plurality of functional blocks from the wafer bank layers; fabricating the interconnect layers on the wafer bank layers; and fabricating the finishing layers on the interconnect layers to produce the integrated circuit. Architectures for these integrated circuits can contain a field programmable gate array that is integrated with a mask programmable gate array in a ring structure.

摘要翻译： 本发明提供了用于混合集成电路的结构和用于产生这些混合集成电路的方法，所述混合集成电路既包含现场可编程门阵列，也包含掩模可编程门阵列，这是一种专用集成电路的形式。 用于制造现场可编程和可编程掩模的集成电路的方法包括以下步骤：设计晶片组层和精加工层，其中晶片组层提供多个可选功能块; 制造所述晶片组层; 设计用于所述集成电路的掩模编程互连层，其中所述互连层将所述多个功能块中的选定的互连层与所述晶片库层相互连接; 制造晶片堤层上的互连层; 以及在互连层上制造精加工层以产生集成电路。 这些集成电路的架构可以包含与环形结构中的掩模可编程门阵列集成的现场可编程门阵列。

公开(公告)号：US08131909B1

公开(公告)日：2012-03-06

申请号：US11857858

申请日：2007-09-19

申请人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

发明人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

IPC分类号： G06F13/00 ,  G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443

摘要： A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

摘要翻译： 使用耦合到可编程逻辑结构的一个或多个信号处理引擎来描述高性能现场可编程门阵列。 每个信号处理引擎包括用于执行指定任务的信号处理单元和用于将基于总线的输入路由到基于总线的输出的基于总线的可配置连接盒。 信号处理单元具有用于计算的浮点单元（FPU）/乘法累加（MAC）和用于存储信息的寄存器文件。 可编程逻辑结构耦合到一个或多个信号处理引擎，用于在信号处理引擎之间路由信息。

公开(公告)号：US07970979B1

公开(公告)日：2011-06-28

申请号：US11857661

申请日：2007-09-19

申请人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

发明人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

IPC分类号： G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F7/483 ,  G06F7/5443 ,  H03K19/17736

摘要： A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

摘要翻译： 使用耦合到可编程逻辑结构的一个或多个信号处理引擎来描述高性能现场可编程门阵列。 每个信号处理引擎包括用于执行指定任务的信号处理单元和用于将基于总线的输入路由到基于总线的输出的基于总线的可配置连接盒。 信号处理单元具有用于计算的浮点单元（FPU）/乘法累加（MAC）和用于存储信息的寄存器文件。 可编程逻辑结构耦合到一个或多个信号处理引擎，用于在信号处理引擎之间路由信息。

公开(公告)号：US20100329262A1

公开(公告)日：2010-12-30

申请号：US12830411

申请日：2010-07-05

申请人： Malcolm J. Wing ,  Jay B. Patel ,  Jeffrey M. Schroeder

发明人： Malcolm J. Wing ,  Jay B. Patel ,  Jeffrey M. Schroeder

IPC分类号： H04L12/56

CPC分类号： H04L43/18 ,  H04L69/12 ,  H04L69/22 ,  H04L69/324

摘要： A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.

摘要翻译： 一种用于解析帧的系统，包括被配置为从第一帧识别第一小区的第一小区提取电路（CEC），可操作地连接到第一CEC的第一解析器引擎，其中第一解析器引擎被配置为基于 第一单元和第一转发电路，其可操作地连接到第一解析器引擎并且被配置为转发结果，其中第一CEC，第一解析器引擎和第一转发电路与第一帧解析器单元相关联。

公开(公告)号：US07757193B2

公开(公告)日：2010-07-13

申请号：US11537744

申请日：2006-10-02

申请人： Bo Hu

发明人： Bo Hu

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5054

摘要： A method for clustering logic units in a field programmable integrated chip to generate a set of clusters is disclosed. The clustering step for forming a super cluster comprises a first logic element and a second logic unit a first logic unit and a super cluster, or a first super cluster and a second super cluster. The method includes generating all possible configurations by enumerating all possible two-way relationships combining a driver-and-receiver relationship from a pool of a finite number of dedicated connections. The set of all possible configurations is reduced to a subset of configurations based on one or more multi-dimension criteria. Each dimension in the multi-dimensional criteria is represented by a parameter. The method involves prioritizing a collection of parameters so that a set of selected parameters or a set of selected criteria is used to generate a desirable number of subsets of configurations.

摘要翻译： 公开了一种用于对现场可编程集成芯片中的逻辑单元进行聚类以产生一组簇的方法。 用于形成超级群集的聚类步骤包括第一逻辑单元和第二逻辑单元，第一逻辑单元和超群集，或第一超群和第二超群。 该方法包括通过枚举从有限数量的专用连接的池组合驱动器和接收器关系的所有可能的双向关系来生成所有可能的配置。 所有可能的配置的集合基于一个或多个多维标准被减少到一个配置的子集。 多维标准中的每个维度都由一个参数表示。 该方法涉及对参数集合进行优先级排序，以便使用一组所选择的参数或一组选择的标准来生成期望数量的配置子集。

公开(公告)号：US07696018B2

公开(公告)日：2010-04-13

申请号：US12116911

申请日：2008-05-07

申请人： Antonietta Oliva ,  Louis Charles Kordus, II ,  Narbeh Derharcobian ,  Vei-Han Chan ,  Thomas E. Stewart, Jr.

发明人： Antonietta Oliva ,  Louis Charles Kordus, II ,  Narbeh Derharcobian ,  Vei-Han Chan ,  Thomas E. Stewart, Jr.

IPC分类号： H01L21/06 ,  H01L45/00

CPC分类号： H01L45/1683 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/126

摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，该相变材料的导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

公开(公告)号：US09665677B2

公开(公告)日：2017-05-30

申请号：US14729829

申请日：2015-06-03

申请人： Agate Logic Inc.

发明人： Suresh Subramanian ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Jason Golbus ,  Dana L. How

IPC分类号： G11C7/00 ,  G06F17/50 ,  G06F13/16 ,  H03K19/177

CPC分类号： G06F17/5054 ,  G06F13/1668 ,  G06F17/505 ,  G06F17/5077 ,  G11C7/00 ,  H03K19/177 ,  Y02D10/14

摘要： A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

公开(公告)号：US20160226491A1

公开(公告)日：2016-08-04

申请号：US14612076

申请日：2015-02-02

申请人： Kai Keung Chan ,  David Tsang ,  Shian-Jiun Fu ,  Chao-Chiang Chen

发明人： Kai Keung Chan ,  David Tsang ,  Shian-Jiun Fu ,  Chao-Chiang Chen

IPC分类号： H03K19/0175 ,  H03K19/177 ,  H03K19/02

CPC分类号： H03K19/017581 ,  H03K19/02 ,  H03K19/17736

摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

摘要翻译： 公开了一种包含专用集成电路（“ASIC”）和现场可编程门阵列（“FPGA”）的逻辑处理装置，能够自动连接ASIC和FPGA。 逻辑处理装置在一个方面包括相位调整电路，ASIC和可配置逻辑电路（“CLC”），其中CLC可以是FPGA。 虽然ASIC能够根据ASIC时钟域执行特定功能，但是CLC能够根据FPGA时钟域执行可编程逻辑功能。 相位调整电路用于根据ASIC时钟域和FPGA时钟域来自动促进ASIC和CLC之间的通信。

公开(公告)号：US08639952B1

公开(公告)日：2014-01-28

申请号：US11716265

申请日：2007-03-09

申请人： Vei-Han Chan ,  Louis Charles Kordus, II

发明人： Vei-Han Chan ,  Louis Charles Kordus, II

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  H03K19/0008 ,  H03K19/1776

摘要： A programmable logic device (PLD) provides voltage identification (VID) codes to a voltage regulator module having VID capabilities. The voltage regulator module generates supply Vdd and/or body bias Vbb voltages according to a selected VID code. The value of the supply Vdd and/or body bias Vbb voltages generated and applied to the PLD determine the operating characteristics of the PLD. The VID codes can be provided and stored in various ways: by an addressable lookup table (LUT) integrated with the PLD, by a memory device in which the VID codes are transferred from an external memory. The VID codes may also be self-generated by auto-detect circuitry integrated with the PLD. The ability to select a particular VID code for each individual PLD allows the user to optimize operational characteristics of the device to satisfy power and/or performance requirements.

摘要翻译： 可编程逻辑器件（PLD）向具有VID功能的电压调节器模块提供电压识别（VID）代码。 电压调节器模块根据选定的VID代码产生电源Vdd和/或体偏置Vbb电压。 生成并施加到PLD的电源Vdd和/或体偏置Vbb电压的值确定PLD的操作特性。 可以以各种方式提供和存储VID代码：通过与PLD集成的可寻址查找表（LUT），其中VID代码从外部存储器传送的存储器件。 VID代码也可以通过与PLD集成的自动检测电路自行生成。 为每个独立PLD选择特定VID代码的能力允许用户优化设备的操作特性以满足功率和/或性能要求。

公开(公告)号：US20120182794A1

公开(公告)日：2012-07-19

申请号：US13433039

申请日：2012-03-28

申请人： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

发明人： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

IPC分类号： G11C11/00

CPC分类号： H01L45/1226 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1683 ,  H03K19/02

摘要： Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device.

摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。 结构允许应用，其中可以在两个有源端子之间产生电连接，并且使用单独的端子或端子来实现连接的控制。因此，加热器元件的电阻可以独立于两者之间的路径的电阻而增加 有源端子，允许使用较小的加热器元件，因此需要更少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。