摘要:
A method for cleaning a through via including the following steps is provided: heating a cleaning fluid to a predetermined temperature; mixing the cleaning liquid with an inert gas and entering into a cleaning cavity; atomizing the cleaning liquid in an atomizer to spray on a wafer surface and to wet an inner wall and a bottom of the through via; and closing a cleaning liquid valve.
摘要:
A TSV exposing process is provided, including: performing a mechanical grinding process on the substrate back surface of a substrate with a TSV conductive column, a liner between the substrate and the TSV conductive column; performing a first and a second chemical mechanical polishing process on the grinded substrate back surface; then performing an etching on the substrate back surface, and making the TSV backside reveal more than 10 μm.
摘要:
A TSV wafer thinning controlling method and system is provided, which can improve the accuracy of the wafer thinning technique. The system includes a chuck table used for carrying a wafer and a grinding device used for thinning the wafer; and further includes: an infrared sensor equipped on the chuck table or grinding device, and a measurement feedback system connected with the infrared sensor and the grinding device; wherein, the infrared sensor comprises an infrared emitting and receiving circuit, signal amplifying and filtering circuit and a data processor.
摘要:
A wafer-level chip structure, a multiple-chip stacked and interconnected structure and a fabricating method thereof, wherein the wafer-level chip structure includes: a through-silicon via, which penetrates a wafer; a first surface including an active region, a multi-layered redistribution layer and a bump; and a second surface including an insulation dielectric layer, and a frustum transition structure connected with the through-silicon via. In an embodiment of the present application, a frustum type impedance transition structure is introduced into a position between a TSV exposed area on a backside of a wafer and a UBM so as to implement an impedance matching between TSV and UBM, thereby alleviating the problem of signal distortion that is caused by an abrupt change of impedance.
摘要:
The present application discloses a fan-out packaging structure and a packaging method for a chip. The structure includes first and second chips with oppositely fitted bottoms; metal terminals distributed around the first chip, one side of the metal terminals being on a same plane with the front of the first chip; a lead connected between the front of the second chip and the other side of the metal terminal; a packaging layer for packaging the first chip, the second chip, the lead the metal terminals; and a lead-out layer disposed on a first surface of the packaging layer and electrically connected to one side of the metal terminals and/or the front of the first chip.
摘要:
The present invention discloses a stress sensor structure and a manufacturing method thereof, wherein the stress sensor structure comprises: a substrate; a blind-hole, provided on a first surface of the substrate; a first piezoresistive layer and a second piezoresistive layer, formed by material with piezoresistive effect, provided on a lateral wall of the blind-hole and interconnected at bottom portions of the layers; a second insulating layer, provided between the first piezoresistive layer and the second piezoresistive layer; a first electrode, provided on the first surface of the substrate and connected to the first piezoresistive layer; a second electrode, provided on the first surface of the substrate and connected to the second piezoresistive layer. The resistance measured by applying an external voltage between the first electrode and the second electrode can be used to indicator a stress of the TSV structure, in particular an axial stress thereof, so that the stress sensor can be used to measure a stress of the TSV structure.
摘要:
An active optical adapter plate comprises a main body, the main body comprises at least a through hole and at least a photoelectric detection area, the through hole is disposed on an end face of the main body and configured to insert an optical fiber to provide an optical path for an emission light of a laser; the photoelectric detection area is disposed on the end face of the main body having the through hole, and comprises a photoelectric detector used for detecting a reflected light of the emission light of the laser and converting the detected reflected light into an electrical signal.
摘要:
A solution for dissipating heat generated from high power chip packages, e.g., a fcBGA package, wbBGA package, 2.5D/3D TSV package, PoP, etc. The heat dissipation system may include a high power chip package including a high power chip. A micro-jet may be attached to the high power chip. A micro-pump may be in fluidic communication with the micro-jet. A heat exchanger may be in fluidic communication with the micro-pump. The high power chip package is assembled on the same PCB with the micro-pump and the heat exchanger.
摘要:
A mechanical debonding method and system are provided. A mechanical debonding method, used to debond temporary bonding wafers formed by bonding a device wafer and a carrier wafer by an adhesive, includes: obtaining the height position of the adhesive through a thickness measurement apparatus; moving a cutting apparatus to a position between the device wafer and the carrier wafer based on the height position of the adhesive, then removing the adhesive at the edge of the temporary bonding wafers by the cutting apparatus; removing the carrier wafer from the temporary bonding wafers; cleaning the adhesive left on the surface of the device wafer.
摘要:
A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (“BEOL”) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer.