公开(公告)号：US20140021610A1

公开(公告)日：2014-01-23

申请号：US13555248

申请日：2012-07-23

申请人： Carsten VON KOBLINSKI ,  Michael KNABL ,  Ursula MEYER ,  Francisco Javier SANTOS RODRIGUEZ ,  Alexander BREYMESSER ,  Andre BROCKMEIER

发明人： Carsten VON KOBLINSKI ,  Michael KNABL ,  Ursula MEYER ,  Francisco Javier SANTOS RODRIGUEZ ,  Alexander BREYMESSER ,  Andre BROCKMEIER

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L23/44 ,  H01L23/3121 ,  H01L23/473 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32237 ,  H01L2224/73267 ,  H01L2224/83411 ,  H01L2224/83418 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83466 ,  H01L2224/83469 ,  H01L2224/83471 ,  H01L2224/83473 ,  H01L2224/83476 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13026 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/83

摘要： A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region.

摘要翻译： 提供芯片封装，芯片封装包括：第一封装结构; 在第一封装结构上形成的第一钝化层和形成在第一钝化层上的第一导电层; 布置在第一导电层和钝化层之上的至少一个芯片，其中至少一个芯片接触焊盘接触第一导电层; 在第一封装结构中形成的至少一个空腔，其中至少一个空腔暴露覆盖至少一个芯片接触焊盘的第一钝化层的一部分; 第二封装结构设置在第一封装结构上并且覆盖至少一个空腔，其中至少一个芯片接触焊盘上的腔室区域由至少一个空腔和第二封装结构限定; 其中第二封装结构包括连接到室区域的入口和出口，其中入口和出口控制散热材料流入和流出室区域。

公开(公告)号：US20120161325A1

公开(公告)日：2012-06-28

申请号：US13349598

申请日：2012-01-13

申请人： Paul Alan McConnelee ,  Arun Virupaksha Gowda

发明人： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC分类号： H01L23/522

CPC分类号： H01L24/82 ,  H01L21/486 ,  H01L24/06 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/2405 ,  H01L2224/2413 ,  H01L2224/24225 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/92144 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13026 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/00

摘要： A semiconductor device package is provided. The semiconductor device package includes a laminate comprising a first metal layer disposed on a dielectric film; a plurality of vias extending through the laminate according to a predetermined pattern; one or more semiconductor devices attached to the dielectric film such that the semiconductor device contacts one or more vias; a patterned interconnect layer disposed on dielectric film, said patterned interconnect layer comprising one or more patterned regions of the first metal layer and an electrically conductive layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device. The patterned interconnect layer comprises a top interconnect region and a via interconnect region, wherein the package interconnect region has a thickness greater than a thickness of the via interconnect region.

摘要翻译： 提供半导体器件封装。 所述半导体器件封装包括：层叠体，其包含设置在电介质膜上的第一金属层; 根据预定图案延伸穿过层压体的多个通孔; 一个或多个半导体器件连接到电介质膜，使得半导体器件接触一个或多个通孔; 设置在电介质膜上的图案化互连层，所述图案化互连层包括第一金属层的一个或多个图案化区域和导电层，其中图案化互连层的一部分延伸穿过一个或多个通孔以形成与 半导体器件。 图案化互连层包括顶部互连区域和通孔互连区域，其中封装互连区域的厚度大于通孔互连区域的厚度。

公开(公告)号：US11876026B2

公开(公告)日：2024-01-16

申请号：US17592161

申请日：2022-02-03

申请人： Medtronic, Inc.

发明人： Chunho Kim ,  Mark E. Henschel

IPC分类号： H01L23/15 ,  H01L21/48 ,  H01L21/56 ,  H01L23/08 ,  H01L23/485 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L23/15 ,  H01L21/486 ,  H01L21/56 ,  H01L23/08 ,  H01L23/485 ,  H01L23/5383 ,  H01L24/14 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/13026 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14

摘要： Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.

公开(公告)号：US20150207442A1

公开(公告)日：2015-07-23

申请号：US14505267

申请日：2014-10-02

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Jun-Ho LEE

IPC分类号： H02P6/14 ,  H01L23/62

CPC分类号： H01L23/62 ,  H01L25/071 ,  H01L2224/48096 ,  H01L2224/48139 ,  H01L2224/49113 ,  H01L2924/1302 ,  H01L2924/13026 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00

摘要： An intelligent power module having a snubber capacitor for surge reduction installed therein is disclosed. IPM having a snubber capacitor according to an embodiment of the present invention can prevent a device from malfunctioning or being destroyed by a surge voltage. An embodiment of the present invention can allow for easy design of the IPM and reduction of an area and cost of a PCB

摘要翻译： 公开了一种具有安装在其中用于浪涌衰减的缓冲电容器的智能功率模块。 根据本发明的实施例的具有缓冲电容器的IPM可以防止装置发生故障或被浪涌电压破坏。 本发明的实施例可以容易地设计IPM并减少PCB的面积和成本

公开(公告)号：US20240145322A1

公开(公告)日：2024-05-02

申请号：US18408812

申请日：2024-01-10

申请人： MEDTRONIC, INC.

发明人： Chunho Kim ,  Mark E. Henschel

IPC分类号： H01L23/15 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/08 ,  H01L23/485 ,  H01L23/538

CPC分类号： H01L23/15 ,  H01L21/486 ,  H01L21/56 ,  H01L23/08 ,  H01L23/485 ,  H01L23/5383 ,  H01L24/14 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/13026 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14

摘要： Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.

公开(公告)号：US09397207B2

公开(公告)日：2016-07-19

申请号：US14828326

申请日：2015-08-17

申请人： David Schie

发明人： David Schie

IPC分类号： H01L29/66 ,  H01L21/332 ,  H01L29/745 ,  H01L29/74

CPC分类号： H02M7/145 ,  H01L27/0921 ,  H01L27/1027 ,  H01L29/102 ,  H01L29/7455 ,  H02M7/1557 ,  H02M2001/4291 ,  H01L2924/1302 ,  H01L2924/13026

摘要： An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (

公开(公告)号：US08114712B1

公开(公告)日：2012-02-14

申请号：US12975466

申请日：2010-12-22

申请人： Paul Alan McConnelee ,  Arun Virupaksha Gowda

发明人： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L24/82 ,  H01L21/486 ,  H01L24/06 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/2405 ,  H01L2224/2413 ,  H01L2224/24225 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/92144 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13026 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device package is provided. The method includes providing a laminate comprising a dielectric film disposed on a first metal layer, said laminate having a dielectric film outer surface and a first metal layer outer surface; forming a plurality of vias extending through the laminate according to a predetermined pattern; attaching one or more semiconductor device to the dielectric film outer surface such that the semiconductor device contacts one or more vias after attachment; disposing an electrically conductive layer on the first metal layer outer surface and on an inner surface of the plurality of vias to form an interconnect layer comprising the first metal layer and the electrically conductive layer; and patterning the interconnect according to a predetermined circuit configuration to form a patterned interconnect layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device. A semiconductor device package is also provided.

摘要翻译： 提供一种制造半导体器件封装的方法。 该方法包括提供一种层叠体，其包含布置在第一金属层上的电介质膜，所述层压体具有电介质膜外表面和第一金属层外表面; 根据预定图案形成延伸穿过层叠体的多个通孔; 将一个或多个半导体器件附接到电介质膜外表面，使得半导体器件在附接之后接触一个或多个通孔; 在所述第一金属层外表面上和所述多个通孔的内表面上设置导电层以形成包括所述第一金属层和所述导电层的互连层; 以及根据预定电路配置图案化所述互连以形成图案化互连层，其中所述图案化互连层的一部分延伸穿过一个或多个通孔以与所述半导体器件形成电接触。 还提供了半导体器件封装。

公开(公告)号：US20160133734A1

公开(公告)日：2016-05-12

申请号：US14828326

申请日：2015-08-17

申请人： DAVID SCHIE

发明人： DAVID SCHIE

IPC分类号： H01L29/745 ,  H01L29/74

CPC分类号： H02M7/145 ,  H01L27/0921 ,  H01L27/1027 ,  H01L29/102 ,  H01L29/7455 ,  H02M7/1557 ,  H02M2001/4291 ,  H01L2924/1302 ,  H01L2924/13026

摘要： An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (

公开(公告)号：US09142657B2

公开(公告)日：2015-09-22

申请号：US14214816

申请日：2014-03-15

申请人： David Schie

发明人： David Schie

IPC分类号： H01L29/66 ,  H01L21/332 ,  H01L29/745 ,  H02M7/155 ,  H01L29/10

CPC分类号： H02M7/145 ,  H01L27/0921 ,  H01L27/1027 ,  H01L29/102 ,  H01L29/7455 ,  H02M7/1557 ,  H02M2001/4291 ,  H01L2924/1302 ,  H01L2924/13026

摘要： An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (

摘要翻译： 提供了一种改进的门控晶闸管，其利用的硅面积小于IGBT，BIPOLAR或MOSFET的尺寸适用于相同的应用。 本发明的晶闸管的实施例具有较低的栅极电荷，以及用于给定电流密度的较低的正向压降。 一旦触发的晶闸管的实施例具有不具有必须从栅极充电的相同Cgd或Ccb电容器的锁存结构，因此门控晶闸管产生更便宜，并且需要较小的栅极驱动器并且占用更少的空间 比标准解决方案。 本发明的晶闸管的实施例提供比使用改进的MCT结构的典型> 600ns更快的关断速度，其导致改进的尾电流关断曲线（<250ns）。 此外，器件的串联电阻降低，而不包括实现电压阻断能力。 最后，教导了正的唯一的栅极驱动装置是使用栅极端子来模拟饱和电流的方法。

公开(公告)号：US20150016165A1

公开(公告)日：2015-01-15

申请号：US14214816

申请日：2014-03-15

申请人： DAVID SCHIE

发明人： DAVID SCHIE

IPC分类号： H01L29/745 ,  H02M1/42 ,  H02M7/155 ,  H01L29/74 ,  H01L29/10

CPC分类号： H02M7/145 ,  H01L27/0921 ,  H01L27/1027 ,  H01L29/102 ,  H01L29/7455 ,  H02M7/1557 ,  H02M2001/4291 ,  H01L2924/1302 ,  H01L2924/13026

摘要： An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (

摘要翻译： 提供了一种改进的门控晶闸管，其利用的硅面积小于IGBT，BIPOLAR或MOSFET的尺寸适用于相同的应用。 本发明的晶闸管的实施例具有较低的栅极电荷，以及用于给定电流密度的较低的正向压降。 一旦触发的晶闸管的实施例具有不具有必须从栅极充电的相同Cgd或Ccb电容器的锁存结构，因此门控晶闸管产生更便宜，并且需要较小的栅极驱动器并且占用更少的空间 比标准解决方案。 本发明的晶闸管的实施例提供比使用改进的MCT结构的典型> 600ns更快的关断速度，其导致改进的尾电流关断曲线（<250ns）。 此外，器件的串联电阻降低，而不包括实现电压阻断能力。 最后，教导了正的唯一的栅极驱动装置是使用栅极端子来模拟饱和电流的方法。