公开(公告)号：US09710181B2

公开(公告)日：2017-07-18

申请号：US15161815

申请日：2016-05-23

Applicant: L. Pierre de Rochemont ,  Alexander J. Kovacs

Inventor： L. Pierre de Rochemont ,  Alexander J. Kovacs

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/10 ,  G06F9/30 ,  G06F13/42 ,  G06F1/28 ,  G06F12/1009 ,  G06F13/36 ,  G06F9/38 ,  G06F12/0875 ,  G06F13/16 ,  G06F13/24 ,  G06F12/0862 ,  G06F12/0815

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the transfer of data between off-chip physical memory and processor die.

公开(公告)号：US20170031847A1

公开(公告)日：2017-02-02

申请号：US15162759

申请日：2016-05-24

Applicant: L. Pierre de Rochemont ,  Alexander J. Kovacs

Inventor： L. Pierre de Rochemont ,  Alexander J. Kovacs

IPC: G06F13/16 ,  G11C7/10 ,  G06F1/32 ,  G06F13/24 ,  G06F9/30

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a hilly integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die.

Abstract translation: 混合片上系统提供了安装在半导体载体芯片上的多个存储器和处理器管芯，其包含以匹配或接近处理器核心时钟速度的速度切换直流电力的丘陵集成电源管理系统，从而允许 片外物理内存与处理器之间的数据死亡。

公开(公告)号：US20170031843A1

公开(公告)日：2017-02-02

申请号：US15162739

申请日：2016-05-24

Applicant: L. Pierre de Rochemont ,  Alexander J. Kovacs

Inventor： L. Pierre de Rochemont ,  Alexander J. Kovacs

IPC: G06F13/16 ,  G06F12/1009 ,  G06F12/0815 ,  G06F12/0862 ,  G06F15/80 ,  G06F13/36 ,  G06F13/42 ,  G06F13/24 ,  G06F9/38 ,  G06F9/30 ,  G06F1/28 ,  G06F12/0875

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die.

Abstract translation: 混合片上系统提供安装在半导体载体芯片上的多个存储器和处理器管芯，其包含完全集成的电源管理系统，其以匹配或接近处理器核心时钟速度的速度切换DC电力，从而允许 片外物理内存与处理器之间的数据死亡。

公开(公告)号：US09766680B2

公开(公告)日：2017-09-19

申请号：US15162745

申请日：2016-05-24

Applicant: L. Pierre de Rochemont

Inventor： L. Pierre de Rochemont

IPC: G06F12/00 ,  G06F1/32 ,  G06F1/26 ,  H01L21/762 ,  H01L21/00 ,  H01L27/02 ,  H01L21/84 ,  H01L25/065 ,  H01L25/16 ,  G06F9/30 ,  G06F9/38 ,  G06F12/1009 ,  G06F13/16 ,  G06F13/24 ,  G11C7/10 ,  G06F1/28 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the transfer of data between off-chip physical memory and processor die.

公开(公告)号：US09011763B2

公开(公告)日：2015-04-21

申请号：US13623459

申请日：2012-09-20

Applicant: Massachusetts Institute of Technology ,  The Trustees of Boston College

Inventor： Gang Chen ,  Mildred Dresselhaus ,  Zhifeng Ren

IPC: B22F3/14 ,  C22C1/04 ,  H01L35/34 ,  H01L35/14 ,  B29C43/36 ,  H01L35/16 ,  H01L35/22

CPC classification number: B29C43/36 ,  H01L35/16 ,  H01L35/22 ,  Y10S257/00 ,  Y10T428/2938

Abstract: The present invention is generally directed to nanocomposite thermoelectric materials that exhibit enhanced thermoelectric properties. The nanocomposite materials include two or more components, with at least one of the components forming nano-sized structures within the composite material. The components are chosen such that thermal conductivity of the composite is decreased without substantially diminishing the composite's electrical conductivity. Suitable component materials exhibit similar electronic band structures. For example, a band-edge gap between at least one of a conduction band or a valence band of one component material and a corresponding band of the other component material at interfaces between the components can be less than about 5kBT, wherein kB is the Boltzman constant and T is an average temperature of said nanocomposite composition.

Abstract translation: 本发明一般涉及显示增强的热电性质的纳米复合热电材料。 纳米复合材料包括两种或多种组分，其中至少一种组分在复合材料内形成纳米尺寸的结构。 选择这些组分使得复合材料的热导率降低而基本上不会降低复合材料的导电性。 合适的组分材料表现出类似的电子带结构。 例如，在一个组分材料的导带或价带中的至少一个与组分之间的界面处的另一组分材料的相应带之间的带边间隙可以小于约5kBT，其中kB是玻尔兹曼 常数，T是所述纳米复合材料组合物的平均温度。

公开(公告)号：US07465871B2

公开(公告)日：2008-12-16

申请号：US10977363

申请日：2004-10-29

Applicant: Gang Chen ,  Zhifeng Ren ,  Mildred Dresselhaus

Inventor： Gang Chen ,  Zhifeng Ren ,  Mildred Dresselhaus

IPC: H01L35/12

CPC classification number: B29C43/36 ,  H01L35/16 ,  H01L35/22 ,  Y10S257/00 ,  Y10T428/2938

Abstract: The present invention is generally directed to nanocomposite thermoelectric materials that exhibit enhanced thermoelectric properties. The nanocomposite materials include two or more components, with at least one of the components forming nano-sized structures within the composite material. The components are chosen such that thermal conductivity of the composite is decreased without substantially diminishing the composite's electrical conductivity. Suitable component materials exhibit similar electronic band structures. For example, a band-edge gap between at least one of a conduction band or a valence band of one component material and a corresponding band of the other component material at interfaces between the components can be less than about 5kBT, wherein kB is the Boltzman constant and T is an average temperature of said nanocomposite composition.

Abstract translation: 本发明一般涉及显示增强的热电性质的纳米复合热电材料。 纳米复合材料包括两种或多种组分，其中至少一种组分在复合材料内形成纳米尺寸的结构。 选择这些组分使得复合材料的热导率降低而基本上不会降低复合材料的导电性。 合适的组分材料表现出类似的电子带结构。 例如，在一个组分材料的导带或价带中的至少一个与组分之间的界面处的另一组分材料的相应带之间的带边间隙可以小于约5kBT，其中kB是玻尔兹曼 常数，T是所述纳米复合材料组合物的平均温度。

公开(公告)号：US20170031413A1

公开(公告)日：2017-02-02

申请号：US15162285

申请日：2016-05-23

Applicant: L. Pierre de Rochemont ,  Alexander J. Kovacs

Inventor： L. Pierre de Rochemont ,  Alexander J. Kovacs

IPC: G06F1/32 ,  G06F13/16 ,  H01L25/16 ,  G06F9/30 ,  G06F9/38 ,  H01L25/065 ,  G06F12/1009 ,  G06F13/24

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core dock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die.

Abstract translation: 混合片上系统提供安装在半导体载体芯片上的多个存储器和处理器管芯，其包含完全集成的电源管理系统，其以匹配或接近处理器核心码头速度的速度切换直流电力，从而允许 片外物理内存与处理器之间的数据死亡。

公开(公告)号：US20140191435A1

公开(公告)日：2014-07-10

申请号：US13623459

申请日：2012-09-20

Applicant: Massachusetts Institute of Technology ,  The Trustees of Boston College

Inventor： Gang Chen ,  Mildred Dresselhaus ,  Zhifeng Ren

IPC: B29C43/36

CPC classification number: B29C43/36 ,  H01L35/16 ,  H01L35/22 ,  Y10S257/00 ,  Y10T428/2938

Abstract: The present invention is generally directed to nanocomposite thermoelectric materials that exhibit enhanced thermoelectric properties. The nanocomposite materials include two or more components, with at least one of the components forming nano-sized structures within the composite material. The components are chosen such that thermal conductivity of the composite is decreased without substantially diminishing the composite's electrical conductivity. Suitable component materials exhibit similar electronic band structures. For example, a band-edge gap between at least one of a conduction band or a valence band of one component material and a corresponding band of the other component material at interfaces between the components can be less than about 5 kBT, wherein kB is the Boltzman constant and T is an average temperature of said nanocomposite composition.

Abstract translation: 本发明一般涉及显示增强的热电性质的纳米复合热电材料。 纳米复合材料包括两种或多种组分，其中至少一种组分在复合材料内形成纳米尺寸的结构。 选择这些组分使得复合材料的热导率降低而基本上不会降低复合材料的导电性。 合适的组分材料表现出类似的电子带结构。 例如，在一个组分材料的导带或价带中的至少一个与组分之间的界面处的另一组分材料的相应带之间的带边间隙可以小于约5kBT，其中kB是 玻尔兹曼常数和T是所述纳米复合组合物的平均温度。

公开(公告)号：US20140013132A1

公开(公告)日：2014-01-09

申请号：US13917607

申请日：2013-06-13

Applicant: L. Pierre de Rochemont ,  Alexander J. Kovacs

Inventor： L. Pierre de Rochemont ,  Alexander J. Kovacs

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die.

Abstract translation: 混合片上系统提供安装在半导体载体芯片上的多个存储器和处理器管芯，其包含完全集成的电源管理系统，其以匹配或接近处理器核心时钟速度的速度切换直流电力，从而允许 片外物理内存与处理器之间的数据死亡。

公开(公告)号：US20180224916A1

公开(公告)日：2018-08-09

申请号：US15845259

申请日：2017-12-18

Applicant: L. Pierre de Rochemont

Inventor： L. Pierre de Rochemont

IPC: G06F1/32 ,  G06F15/80 ,  G06F1/28 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  H01L27/02 ,  H01L25/16 ,  H01L25/065 ,  H01L21/84 ,  H01L21/762 ,  H01L21/00 ,  G11C7/10 ,  G06F1/26 ,  G06F13/42 ,  G06F13/36 ,  G06F13/24 ,  G06F13/16 ,  G06F12/1009

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die.