公开(公告)号：WO2021198805A1

公开(公告)日：2021-10-07

申请号：PCT/IB2021/051777

申请日：2021-03-03

Applicant: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： XU, Xiangming ,  ALSHAREEF, Husam Niman

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/02422 ,  H01L21/02428 ,  H01L21/02491 ,  H01L21/02529 ,  H01L21/0254

Abstract: There is a method for making a high-performance opto-electronic device (1300) on an amorphous substrate. The method includes growing (1600) on a single-crystal substrate (1304), a single-crystal, oxide film (1302); applying a first chemical processing (1602) to the single-crystal, oxide film (1302) to obtain a first transferrable, single-crystal, chalcogenide film (1308); transferring (1604) the transferrable, single crystal, chalcogenide film (1308) from the single-crystal substrate (1304) to an amorphous substrate or polycrystalline metal substrate (1316); applying a second chemical processing (1606) to the transferrable, single-crystal, chalcogenide film (1308) to obtain a single-crystal, non-oxide film (1320), wherein the single-crystal, non-oxide film (1320) is different from the transferrable, single-crystal, chalcogenide film (1308); and growing (1608) a wide-bandgap semiconductor film (1324) using the single-crystal, non-oxide film (1320) as a seeding layer to obtain the opto-electronic device (1300) on the amorphous glass or polycrystalline metal substrate. The first chemical processing is different from the second chemical processing.

公开(公告)号：WO2021196974A1

公开(公告)日：2021-10-07

申请号：PCT/CN2021/079157

申请日：2021-03-04

Applicant: 华为技术有限公司

Inventor： 陈智斌

IPC: H01L21/02 ,  H01L21/0254 ,  H01L21/02587 ,  H01L29/0684 ,  H01L29/7786

Abstract: 本申请提供一种半导体外延结构及半导体器件。所述半导体外延结构包括沟道层、复合势垒层和掺杂层，所述掺杂层设于所述复合势垒层上，所述沟道层位于所述复合势垒层背离所述掺杂层一侧，所述复合势垒层包括层叠设置的数字合金势垒层和AlGaN势垒层，所述数字合金势垒层中包括一层或多层AlN层。本申请提供的半导体外延结构有效避免p-GaN层中Mg离子扩散到势垒层和沟道层，影响二维电子气的密度和迁移率，导致导通电阻上升的问题。

公开(公告)号：WO2023002466A2

公开(公告)日：2023-01-26

申请号：PCT/IB2022/058992

申请日：2022-09-22

Applicant: IQE PLC

Inventor： KAESS, Felix ,  KAO, Chen-Kai ,  LABOUTIN, Oleg

IPC: H01L21/20 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7787

Abstract: A high electron mobility transistor 22 comprising a nucleation layer 14 having a first lattice constant, a back-barrier layer 24 having a second lattice constant and a stress management layer 26 having a third lattice constant which is larger than both first and second lattice constants. The stress management layer 26 compensates some or all of the stress due to the lattice mismatch between the nucleation layer 14 and back barrier layer 24 so that the resulting structure experiences less bow and warp.

公开(公告)号：WO2022240716A2

公开(公告)日：2022-11-17

申请号：PCT/US2022/028264

申请日：2022-05-09

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： CHAN, Philip ,  DENBAARS, Steven P. ,  NAKAMURA, Shuji

IPC: H01L21/205 ,  C30B25/10 ,  H01L21/02 ,  H01L33/04 ,  H01L33/12 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/7806 ,  H01L33/007 ,  H01S2301/173 ,  H01S5/0216 ,  H01S5/0217 ,  H01S5/04253 ,  H01S5/2068 ,  H01S5/22 ,  H01S5/3063 ,  H01S5/3213 ,  H01S5/34333

Abstract: A III-nitride based device is fabricated having an in-plane lattice constant or strain that is more than 30% biaxially relaxed, by creating a III-nitride based decomposition stop layer on or above a III-nitride based decomposition layer, wherein a temperature is increased to decompose the III-nitride based decomposition layer; and growing a III-nitride based device structure on or above the III-nitride based decomposition stop layer. The III-nitride based device structure includes at least one of an n-type layer, active layer, and p-type layer, and at least one of the n-type layer, active layer and p-type layer has an in-plane lattice constant or strain that is preferably more than 30% biaxially relaxed, more preferably 50% or more biaxially relaxed, and most preferably at least 70% biaxially relaxed.

公开(公告)号：WO2022056138A2

公开(公告)日：2022-03-17

申请号：PCT/US2021/049679

申请日：2021-09-09

Applicant: RAYTHEON COMPANY

Inventor： SORIC, Jason C. ,  LAROCHE, Jeffrey R. ,  CHUMBES, Eduardo M. ,  PECZALSKI, Adam E.

IPC: H03H9/05 ,  H03H3/02 ,  H03H9/17 ,  H03H9/56 ,  H03H3/04 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02378 ,  H01L21/0254 ,  H01L27/20 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H03F2200/294 ,  H03F2200/451 ,  H03F3/195 ,  H03H2003/023 ,  H03H2003/0442 ,  H03H9/0542 ,  H03H9/174 ,  H03H9/545 ,  H03H9/562 ,  H03H9/564 ,  H03H9/568 ,  H04B1/06 ,  H04B1/10

Abstract: Embodiments of a single-chip ScAIN tunable filter bank include a plurality of switching elements, and a plurality of channel filters integrated on a monolithic platform. The monolithic platform comprises a single crystal base (202) and each of the switching elements comprises at least one of a scandium aluminum nitride (ScAIN) or other Group Ill-Nitride transistor structure (204) fabricated on the single crystal base (202). In these embodiments, each channel filter comprises a multi-layered ScAIN structure (206) comprising one or more a single-crystal epitaxial ScAIN layers fabricated on the single crystal base (202). The ScAIN layers for each channel filter are based on desired frequency characteristics of an associated one of the RF channels.

公开(公告)号：WO2021148808A1

公开(公告)日：2021-07-29

申请号：PCT/GB2021/050152

申请日：2021-01-22

Applicant: PORO TECHNOLOGIES LTD

Inventor： ALI, Muhammad ,  LIU, Yingjun ,  ZHU, Tongtong

IPC: H01L33/16 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/0254 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32

Abstract: A red-light emitting diode (LED) comprises: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and a p-doped portion. The light emitting region comprises: a light-emitting indium gallium nitride layer which emits light at a peak wavelength between 600 and 750 nm under electrical bias thereacross; a Ill-nitride layer located on the light-emitting indium gallium nitride layer; and a III-nitride barrier layer located on the Ill-nitride layer, and the light emitting diode comprises a porous region of III-nitride material. A red mini LED, a red micro-LED, an array of micro-LEDs, and a method of manufacturing a red LED are also provided.

公开(公告)号：WO2021120143A1

公开(公告)日：2021-06-24

申请号：PCT/CN2019/126861

申请日：2019-12-20

Applicant: 电子科技大学

Inventor： 徐跃杭 ,  王衍 ,  吴韵秋

IPC: H01L21/335 ,  H01L21/02378 ,  H01L21/0254 ,  H01L23/3738 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778

Abstract: 一种柔性微波功率晶体管及其制备方法。所述制备方法针对现有的制备方法中Si衬底制备的器件晶格失配大，器件性能不好的技术缺陷，在刚性SiC衬底上生长GaN HEMT层，避免了硅衬底与GaN的晶格失配，提高柔性微波功率晶体管的性能。而且，针对现有的制备方法中存在的输出功率、功率附加效率及功率增益低等问题，通过保留部分刚性SiC衬底，并配合常温生长柔性衬底工艺，实现了高质量器件的制备。相比于传统方法，功率输出能力得到很大提升，效率和增益也大幅度增加，在0.75％应力下，器件性能基本不变。

公开(公告)号：WO2023046427A1

公开(公告)日：2023-03-30

申请号：PCT/EP2022/074082

申请日：2022-08-30

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： LUGAUER, Hans-Jürgen ,  AVRAMESCU, Adrian Stefan ,  HOFFMANN, Marc ,  KUELLER, Viola Miran ,  FORONDA, Humberto ,  BRANDL, Christian

IPC: H01L21/02 ,  H01L21/0242 ,  H01L21/02428 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02667

Abstract: Es wird ein Verfahren zur Herstellung eines Wachstumssubstrats mit den folgenden Schritten angegeben: - Bereitstellen eines polykristallinen Substrats, welches ein Nitridverbindungshalbleitermaterial aufweist, - Aufbringen zumindest einer Oberflächenschicht auf eine Hauptfläche des polykristallinen Substrats, wobei - die zumindest eine Oberflächenschicht ein Nitridverbindungshalbleitermaterial aufweist, und - die zumindest eine Oberflächenschicht zum epitaktischen Aufwachsen einer epitaktischen Halbleiterschichtenfolge eingerichtet ist, - Hochtemperaturtempern des polykristallinen Substrats mit der darauf aufgebrachten zumindest einen Oberflächenschicht. Des Weiteren werden ein Wachstumssubstrat und ein Verfahren zur Herstellung einer Vielzahl optoelektronischer Halbleiterchips angegeben.

公开(公告)号：WO2022115683A2

公开(公告)日：2022-06-02

申请号：PCT/US2021/060973

申请日：2021-11-29

Applicant: CRYSTAL TECHNOLOGIES LLC

Inventor： RAVI, Tirunelveli Subramaniam ,  GOGOI, Bishnu Prasanna

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/04 ,  H01L21/18 ,  H01L21/20 ,  H01L21/30 ,  H01L21/302 ,  H01L21/304 ,  H01L21/02019 ,  H01L21/02271 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/7806

Abstract: In various embodiments methods for manufacturing low-cost wide band gap semiconductor devices are disclosed. In one embodiment, a method includes providing SiC substrate, etching the substrate to form patterned trenches from the defined patterned openings, removing the hard mask using a chemical process, cleaning the substrate with the patterned trenches, performing a buffer epitaxy on the substrate to form a uniform single crystal layer over the patterned trenches to create a plurality of micro voids, performing another epitaxy on the substrate using a fast epitaxial growth process to provide an active device epitaxial layer with high quality suitable to fabricate SiC devices, and after fabrication of the SiC devices, severing the two epitaxial layers with the device layer at the plurality of micro voids. Other embodiments are described and claimed.

公开(公告)号：WO2021255426A1

公开(公告)日：2021-12-23

申请号：PCT/GB2021/051485

申请日：2021-06-15

Applicant: UNIVERSITY OF LANCASTER

Inventor： CARRINGTON, Peter ,  DELLI, Evangelia

IPC: H01L21/20 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549

Abstract: A semiconductor device comprises a substrate, one or more first III- semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.