公开(公告)号：WO2010135168A2

公开(公告)日：2010-11-25

申请号：PCT/US2010/034831

申请日：2010-05-14

Applicant: MICRON TECHNOLOGY, INC. ,  SANDHU, Gurtej ,  SILLS, Scott

Inventor： SANDHU, Gurtej ,  SILLS, Scott

IPC: H01L21/768

CPC classification number: H01L27/10885 ,  H01L21/28008 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2224/06138 ,  H01L2924/12044

Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

Abstract translation: 集成电路和形成方法提供形成在至少一个线性延伸导线的成角度端的接触区域。 在一个实施例中，具有接触着陆焊盘的导电线通过在掩模材料中图案化线形成，切割至少一条材料线以相对于材料线的延伸方向形成一角度，从所述材料线的成角度的端面形成延伸部 掩模材料，并通过使用所述材料线和延伸作为掩模进行蚀刻来图案化下面的导体。 在另一个实施例中，至少一条导线相对于导线的延伸方向以一定角度切割，以产生成角度的端面，并且电接触着陆垫形成为与成角度的端面接触。

公开(公告)号：WO2008137478A2

公开(公告)日：2008-11-13

申请号：PCT/US2008062097

申请日：2008-04-30

Applicant: DSM SOLUTIONS INC ,  KAPOOR ASHOK ,  VORA MADHUKAR B

Inventor： KAPOOR ASHOK ,  VORA MADHUKAR B

IPC: H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/2257 ,  H01L21/28525 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/7843

Abstract: Process for fabrication of MOS semiconductor structures and transistors such as CMOS structures and transistors with thin gate oxide, polysilicon surface contacts having thickness on the order of 500 Angstroms or less and with photo-lithographically determined distances between the gate surface contact and the source and drain contacts. Semiconductor devices having polysilicon surface contacts wherein the ratio of the vertical height to the horizontal dimension is approximately unity. Small geometry Metal-Oxide-Semiconductor (MOS) transistor with thin polycrystalline surface contacts and method and process for making the MOS transistor. MOS and CMOS transistors and process for making. Process for making transistors using Silicon Nitride layer to achieve strained Silicon substrate. Strained Silicon devices and transistors wherein fabrication starts with strained Silicon substrate. Strained Silicon devices which use a Silicon Nitride film applied to the substrate at high temperature and which use differential thermal contraction rates during cooling to achieve strained Silicon.

Abstract translation: 用于制造MOS半导体结构和晶体管如CMOS结构和具有薄栅极氧化物的晶体管的工艺，多晶硅表面触点具有约500埃或更小的厚度，并且具有光刻确定的栅极表面触点与源极和漏极之间的距离 联系人。 具有多晶硅表面接触的半导体器件，其中垂直高度与水平尺寸之比近似为1。 具有薄多晶表面接触的小尺寸金属氧化物半导体（MOS）晶体管以及用于制造MOS晶体管的方法和工艺。 MOS和CMOS晶体管以及制造工艺。 使用氮化硅层制造晶体管以获得应变硅衬底的工艺。 应变硅器件和晶体管，其中制造从应变硅衬底开始。 在高温下使用氮化硅膜的应变硅器件在冷却过程中使用不同的热收缩率来获得应变硅。

公开(公告)号：WO2007136556A3

公开(公告)日：2008-07-03

申请号：PCT/US2007011207

申请日：2007-05-08

Applicant: MARVELL WORLD TRADE LTD ,  SUTARDJA SEHAT

Inventor： SUTARDJA SEHAT

IPC: H01L27/02

CPC classification number: H01L27/0207 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0203 ,  H01L27/088 ,  H01L27/105 ,  H01L29/41758 ,  H01L29/4238

Abstract: An integrated circuit comprises a first source, a first drain, a second source, a first gate arranged between the first source and the first drain, and a second gate arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the drain. The first and second gates are arranged farther apart in the first regions than in the second regions.

Abstract translation: 集成电路包括第一源极，第一漏极，第二源极，布置在第一源极和第一漏极之间的第一栅极，以及布置在第一漏极和第二源极之间的第二栅极。 第一和第二栅极限定漏极中交替的第一和第二区域。 第一和第二栅极在第一区域中比在第二区域中分开更远。

公开(公告)号：WO2007082199A3

公开(公告)日：2007-11-29

申请号：PCT/US2007060265

申请日：2007-01-09

Applicant: IBM ,  ZHU HUILONG

Inventor： ZHU HUILONG

IPC: H01L23/48

CPC classification number: H01L21/28052 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S257/92 ,  H01L2924/00

Abstract: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits comprise a contact line (500, 1300), a gate (310, 1210) situated proximate the contact line (500, 1300). The contact line (500, 1300) comprises a height that is less than the height of the gate (310, 1210). The MOSFET circuits further comprise gate spacers (710, 715, 1610, 1615) situated proximate the gate (310, 1210) and no contact line spacer situated proximate the contact line (500, 1300) and between the contact line (500, 1300) and the gate (310, 1210).

Abstract translation: 本文的实施例呈现用于制造具有不同高度接触线的高密度MOSFET电路的结构，方法等。 MOSFET电路包括接触线（500,1300），位于接触线（500,1300）附近的栅极（310,1210）。 接触线（500,1300）包括小于浇口（310,1210）的高度的高度。 MOSFET电路进一步包括位于栅极（310,1210）附近并且不位于接触线（500,1300）附近和接触线（500,1300）之间的接触线间隔件的栅极间隔件（710,715,1610,1615） 和门（310,1210）。

公开(公告)号：WO2007068714A2

公开(公告)日：2007-06-21

申请号：PCT/EP2006069648

申请日：2006-12-13

Applicant: INFINEON TECHNOLOGIES AG ,  KLEE VEIT ,  KNOEFLER ROMAN ,  SCHROEDER PAUL UWE

Inventor： KLEE VEIT ,  KNOEFLER ROMAN ,  SCHROEDER PAUL UWE

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/60 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

Abstract: To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.

Abstract translation: 为了形成半导体器件，在导电区域上方形成绝缘层，并且在绝缘层上方形成图案转印层。 图案转印层被图案化为将形成在绝缘层中的凹陷的布局的相反色调，使得图案转印层保留在将要形成凹陷的区域上方。 掩模材料形成在绝缘层上并与图案转印层对齐。 使用掩模材料作为掩模，去除图案转印层的剩余部分并在绝缘层中蚀刻凹槽。

公开(公告)号：WO2007033337A2

公开(公告)日：2007-03-22

申请号：PCT/US2006/035876

申请日：2006-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  MARSHALL, Andrew ,  GELSOMINI, Tito ,  DAVIS, Harvey, Edd

Inventor： MARSHALL, Andrew ,  GELSOMINI, Tito ,  DAVIS, Harvey, Edd

IPC: H01L21/3205

CPC classification number: H01L21/76897 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/66492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one aspect, the method of manufacturing a transistor device includes providing a gate structure over a substrate (110). An insulating layer (310) is formed over the gate structure, and openings (710) to the substrate are formed therein, thereby removing a portion of the gate structure. The openings are filled with a conductor (1410), thereby forming an interconnect.

Abstract translation: 本发明提供一种制造晶体管器件的方法，晶体管器件和用于制造集成电路的方法。 一方面，制造晶体管器件的方法包括在衬底（110）上提供栅极结构。 绝缘层（310）形成在栅极结构上方，并且在其中形成到基板的开口（710），从而去除栅极结构的一部分。 开口填充有导体（1410），从而形成互连。

公开(公告)号：WO2007029289A1

公开(公告)日：2007-03-15

申请号：PCT/JP2005/016042

申请日：2005-09-01

Applicant: 富士通株式会社 ,  佐次田 直也

Inventor： 佐次田 直也

IPC: H01L21/8246 ,  H01L27/105

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L21/76895 ,  H01L27/11507 ,  H01L28/55

Abstract: 　強誘電体キャパシタの下部電極下に形成される自己配向膜と、その下の導電性プラグとの間に、厚さが１０ｎｍ以下の薄い酸化アルミニウム膜を形成し、前記自己配向膜に対する導電性プラグ中の結晶粒の配向の影響を遮断し、さらに前記酸化アルミニウム膜上に薄い窒化膜を形成し、自己配向膜中の金属元素が酸化膜表面の酸素に捕獲されて初期の自己配向性が発現しなくなる問題を回避する。

Abstract translation: 在强电介质电容器的下电极下形成的自对准膜与自对准膜下面的导电性塞子之间形成厚度不大于10nm的薄氧化铝膜，以阻止晶体取向的影响 在自对准膜上的导电塞中的颗粒。 此外，在氧化铝膜上形成薄的氮化物膜，以避免氧化膜表面上的氧被自动对准膜中的金属元素捕获的问题，使得初始自对准性不可能为 发达。

公开(公告)号：WO2007017803A2

公开(公告)日：2007-02-15

申请号：PCT/IB2006052644

申请日：2006-08-02

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  ZAWILSKI PETER ,  THEEUWEN STEPHAN J C H ,  VAN RIJS FREERK ,  HAMMES PETRA C A

Inventor： THEEUWEN STEPHAN J C H ,  VAN RIJS FREERK ,  HAMMES PETRA C A

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/41758 ,  H01L21/76895 ,  H01L23/4827 ,  H01L23/53219 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/456 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and a drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2µm. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS transistor (1) further.

Abstract translation: 本发明的LDMOS晶体管（1）包括基板（2），栅极电极（10），基板接触区域（11），源极区域（3），沟道区域（4）和漏极区域 ），该漏极区（5）包括漏极接触区（6）和漏极延伸区（7）。 漏极接触区域（6）电连接到在漏极延伸区域（7）上延伸的顶部金属层（23），顶部金属层（23）和漏极延伸区域（23）之间的距离（723） 7）大于2μm。 这样可以减小漏极接触区域（6）的面积，并且增加LDMOS晶体管（1）的RF功率输出效率。 在另一个实施例中，源极区（3）经由硅化物层（32）而不是第一金属层（21）电连接到衬底接触区（11），从而减小源区（3）和 漏极区域（5），从而进一步提高LDMOS晶体管（1）的RF功率输出效率。

公开(公告)号：WO2005109491B1

公开(公告)日：2006-01-05

申请号：PCT/US2005014951

申请日：2005-04-28

Applicant: MICRON TECHNOLOGY INC

Inventor： TRAN LUAN C ,  FISHBURN FRED D

IPC: H01L21/768 ,  H01L27/105

CPC classification number: H01L21/7681 ,  H01L21/76895 ,  H01L21/823475

Abstract: The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has a pair of openings extending through it, with the openings being along a row substantially parallel to an axis of the line. An insulative material is formed over the etch stop. The insulative material is exposed to an etch to form a trench within the insulative material, and to extend the openings from the etch stop to the diffusion regions. At least a portion of the trench is directly over the openings and extends along the axis of the line. An electrically conductive material is formed within the openings and within the trench.

Abstract translation: 本发明包括用于形成与半导体结构相关联的电连接的方法。 提供了一种在其上具有导线的半导体衬底，并且具有与导电线相邻的至少两个扩散区域。 在扩散区域上形成图案化的蚀刻停止层。 图案化蚀刻停止件具有延伸穿过其的一对开口，其中开口沿着大致平行于该线的轴线。 在蚀刻停止点上形成绝缘材料。 绝缘材料暴露于蚀刻以在绝缘材料内形成沟槽，并且将开口从蚀刻停止件延伸到扩散区域。 沟槽的至少一部分直接在开口上方并且沿着线的轴线延伸。 在开口内和沟槽内形成导电材料。

公开(公告)号：WO2004017414A1

公开(公告)日：2004-02-26

申请号：PCT/US2003/023557

申请日：2003-07-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES L.L.C.

Inventor： GRIVNA, Gordon, M.

IPC: H01L29/735

CPC classification number: H01L29/7816 ,  H01L21/28114 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76895 ,  H01L29/1095 ,  H01L29/41 ,  H01L29/41708 ,  H01L29/42376 ,  H01L29/66272 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/7835

Abstract: A method of making a semiconductor device (10) includes depositing a first conductive layer (50) on a first vertical surface (41) of a multilayer structure (17, 18, 19, 20) formed on a horizontal surface of a semiconductor substrate (14, 16). The first conductive layer (50) controls a channel (70) of the semiconductor device at a second surface (40) perpendicular to the first surface. The method further includes forming first dielectric film (32) between the first conductive layer (50) and the vertical surface on the multilayer, etching it to form a gap (53) between the first conductive layer (50) and a control electrode (68) formed in the multilayer structure and depositing a conductive material (56) in the gap to electrically connect the first conductive layer to the control electrode.

Abstract translation: 制造半导体器件（10）的方法包括在形成在半导体衬底的水平表面上的多层结构（17,18,19,20）的第一垂直表面（41）上沉积第一导电层（50） 14，16）。 第一导电层（50）在垂直于第一表面的第二表面（40）处控制半导体器件的通道（70）。 该方法还包括在第一导电层（50）和多层之间的垂直表面之间形成第一介电膜（32），蚀刻它以在第一导电层（50）和控制电极（68）之间形成间隙 ），并且在所述间隙中沉积导电材料（56）以将所述第一导电层与所述控制电极电连接。