公开(公告)号：WO2008137478A2

公开(公告)日：2008-11-13

申请号：PCT/US2008062097

申请日：2008-04-30

Applicant: DSM SOLUTIONS INC ,  KAPOOR ASHOK ,  VORA MADHUKAR B

Inventor： KAPOOR ASHOK ,  VORA MADHUKAR B

IPC: H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/2257 ,  H01L21/28525 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/7843

Abstract: Process for fabrication of MOS semiconductor structures and transistors such as CMOS structures and transistors with thin gate oxide, polysilicon surface contacts having thickness on the order of 500 Angstroms or less and with photo-lithographically determined distances between the gate surface contact and the source and drain contacts. Semiconductor devices having polysilicon surface contacts wherein the ratio of the vertical height to the horizontal dimension is approximately unity. Small geometry Metal-Oxide-Semiconductor (MOS) transistor with thin polycrystalline surface contacts and method and process for making the MOS transistor. MOS and CMOS transistors and process for making. Process for making transistors using Silicon Nitride layer to achieve strained Silicon substrate. Strained Silicon devices and transistors wherein fabrication starts with strained Silicon substrate. Strained Silicon devices which use a Silicon Nitride film applied to the substrate at high temperature and which use differential thermal contraction rates during cooling to achieve strained Silicon.

Abstract translation: 用于制造MOS半导体结构和晶体管如CMOS结构和具有薄栅极氧化物的晶体管的工艺，多晶硅表面触点具有约500埃或更小的厚度，并且具有光刻确定的栅极表面触点与源极和漏极之间的距离 联系人。 具有多晶硅表面接触的半导体器件，其中垂直高度与水平尺寸之比近似为1。 具有薄多晶表面接触的小尺寸金属氧化物半导体（MOS）晶体管以及用于制造MOS晶体管的方法和工艺。 MOS和CMOS晶体管以及制造工艺。 使用氮化硅层制造晶体管以获得应变硅衬底的工艺。 应变硅器件和晶体管，其中制造从应变硅衬底开始。 在高温下使用氮化硅膜的应变硅器件在冷却过程中使用不同的热收缩率来获得应变硅。

公开(公告)号：WO2008055095A3

公开(公告)日：2008-09-12

申请号：PCT/US2007082815

申请日：2007-10-29

Applicant: DSM SOLUTIONS INC ,  VORA MADHUKAR B

Inventor： VORA MADHUKAR B

IPC: H01L21/337 ,  H01L21/761 ,  H01L27/098 ,  H01L29/808

CPC classification number: H01L29/808 ,  H01L27/098 ,  H01L29/66901

Abstract: An integrated Junction Field Effect Transistor is disclosed which is much smaller and much less expensive to fabricate because it does not use Shallow Trench Isolation or field oxide in the semiconductor substrate to isolate separate transistors. Instead, a layer of insulating material is formed on the top surface of said substrate, and interconnect trenches are etched in said insulating layer which do not go all the way down to the semiconductor substrate. Contact openings are etched in the insulating layer all the way down to the semiconductor layer. Doped poly-silicon is formed in the contact openings and interconnect trenches and silicide is formed on tops of the poly-silicon. This contact and interconnect structure applies to any integrated transistor. The integrated JFET disclosed herein does not use STI or field oxide and uses junction isolation. A conventional JFET is built in a P- well. The P- well is encapsulated in an N-well which is implanted into the substrate. Separate contacts to the P-well, N-well and substrate are formed as well as to the source, drain and gate so that the device can be isolated by reverse-biasing a PN junction. Operating voltage is restricted to less than 0.7 volts to prevent latching.

Abstract translation: 公开了一种集成的结型场效应晶体管，其制造起来小得多并且便宜得多，因为它不在半导体衬底中使用浅沟槽隔离或场氧化物来隔离单独的晶体管。 取而代之的是，在所述衬底的顶表面上形成绝缘材料层，并且在所述绝缘层中蚀刻互连沟槽，所述绝缘层不一直向下到半导体衬底。 接触开口在绝缘层中一直蚀刻到半导体层。 在接触开口和互连沟槽中形成掺杂的多晶硅，并且在多晶硅的顶部形成硅化物。 这种接触和互连结构适用于任何集成晶体管。 这里公开的集成JFET不使用STI或场氧化物并使用结隔离。 传统的JFET是建在一个P-井。 将P阱封装在注入衬底中的N阱中。 形成与P阱，N阱和衬底分开的触点以及源极，漏极和栅极，从而可以通过反向偏置PN结来隔离器件。 工作电压限制在0.7伏以下，以防止锁定。

公开(公告)号：WO2010011536A3

公开(公告)日：2010-04-01

申请号：PCT/US2009050634

申请日：2009-07-15

Applicant: DSM SOLUTIONS INC ,  KAPOOR ASHOK K ,  VORA MADHUKAR B

Inventor： KAPOOR ASHOK K ,  VORA MADHUKAR B

IPC: H01L29/80

CPC classification number: H01L29/8086 ,  H01L29/458 ,  H01L29/66901

Abstract: A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of suicide. The second connection region is in ohmic contact with the drain region and formed of suicide. The third connection region in ohmic contact with the gate region.

Abstract translation: 结型场效应晶体管包括半导体衬底和形成在衬底中的阱区。 在阱区中形成第一导电类型的源极区域。 第一导电类型的漏极区域形成在阱区域中并且与源极区域间隔开。 第一导电类型的沟道区域位于源极区域和漏极区域之间并且形成在阱区域中。 在阱区中形成第二导电类型的栅极区域。 晶体管还包括第一，第二和第三连接区域。 第一连接区域与源区域欧姆接触并形成自杀剂。 第二连接区域与漏极区域欧姆接触并由硅化物形成。 第三连接区域与栅极区域欧姆接触。

公开(公告)号：WO2008137480A2

公开(公告)日：2008-11-13

申请号：PCT/US2008/062101

申请日：2008-04-30

Applicant: DSM SOLUTIONS, INC. ,  VORA, Madhukar, B.

Inventor： VORA, Madhukar, B.

IPC: H01L21/761

CPC classification number: H01L29/808 ,  H01L21/28525 ,  H01L21/761 ,  H01L21/76895 ,  H01L21/8213 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/1066 ,  H01L29/665 ,  H01L29/7833

Abstract: Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to isolate active areas. Insulating layer is formed on top surface of substrate and interconnect channels are etched in insulating layer which do not go down to the semiconductor substrate. Contact openings for surface contacts to wells and substrate are etched in insulating layer down to semiconductor layer. Doped silicon or metal is formed in contact openings for surface contacts and to form interconnects in channels. Silicide may be formed on top of polycrystalline silicon contacts and interconnect lines to lower resistivity. Any JFET or MOS transistor may be integrated into the resulting junction isolated active area.

Abstract translation: 用于晶体管的集成有源区隔离结构来代替更大和更昂贵的浅沟槽隔离或场氧化物来隔离晶体管。 在井之间形成PN结，并且与衬底和阱的表面接触形成多阱注入，因此施加到反向偏置PN结的偏置电压以隔离有源区。 绝缘层形成在衬底的顶表面上，互连通道被蚀刻在绝缘层中，绝缘层不会下降到半导体衬底。 用于与阱和衬底的表面接触的接触开口在绝缘层中被蚀刻到半导体层。 掺杂的硅或金属形成在用于表面接触的接触开口中并且在通道中形成互连。 可以在多晶硅触点和互连线之上形成硅化物以降低电阻率。 任何JFET或MOS晶体管可以集成到所得到的结隔离有源区域中。

公开(公告)号：WO2008137478A3

公开(公告)日：2008-11-13

申请号：PCT/US2008/062097

申请日：2008-04-30

Applicant: DSM SOLUTIONS, INC. ,  KAPOOR, Ashok ,  VORA, Madhukar, B.

Inventor： KAPOOR, Ashok ,  VORA, Madhukar, B.

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/336 ,  H01L29/78

Abstract: Process for fabrication of MOS semiconductor structures and transistors such as CMOS structures and transistors with thin gate oxide, polysilicon surface contacts having thickness on the order of 500 Angstroms or less and with photo-lithographically determined distances between the gate surface contact and the source and drain contacts. Semiconductor devices having polysilicon surface contacts wherein the ratio of the vertical height to the horizontal dimension is approximately unity. Small geometry Metal-Oxide-Semiconductor (MOS) transistor with thin polycrystalline surface contacts and method and process for making the MOS transistor. MOS and CMOS transistors and process for making. Process for making transistors using Silicon Nitride layer to achieve strained Silicon substrate. Strained Silicon devices and transistors wherein fabrication starts with strained Silicon substrate. Strained Silicon devices which use a Silicon Nitride film applied to the substrate at high temperature and which use differential thermal contraction rates during cooling to achieve strained Silicon.

公开(公告)号：WO2007024774A2

公开(公告)日：2007-03-01

申请号：PCT/US2006/032592

申请日：2006-08-22

Applicant: VORA, Madhukar, B.

Inventor： VORA, Madhukar, B.

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/00

Abstract: Self-alignment structures, such as micro-balls (608) and V-grooves (606), may be formed on chips (605, 607) made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads (803, 807) having a pitch of 0.6 microns, compared to a pitch of 100 microns available with today's Ball Grid Array (BGA) technology. As a result, circuits in the mated chips (605, 607) can communicate via the pads (803, 807) with the same speed or clock frequency as if in a single chip. For example, clock rates between interconnected chips (605, 607) can be increased from 100 MHz to 4 GHz due to low capacitance of the interconnected pads (803, 807). Because high-density arrays of pads (803, 807) can interconnect chips, chips (605, 607) can be made smaller, thereby reducing cost of chips (605, 607) by order(s) of magnitude.

Abstract translation: 可以在由不同工艺制成的芯片（605,607）上形成诸如微球（608）和V形槽（606）之类的自对准结构。 自对准结构可以在芯片内的最小特征尺寸的二分之一的精度内对准掩模层。 例如，与目前的球栅阵列（BGA）技术可用的100微米的间距相比，对准结构可以对准具有0.6微米间距的焊盘阵列（803,807）。 结果，配合芯片（605,607）中的电路可以通过焊盘（803,807）以与单个芯片中相同的速度或时钟频率进行通信。 例如，由于互连焊盘（803,807）的低电容，互连芯片（605,607）之间的时钟速率可以从100MHz增加到4GHz。 由于焊盘的高密度阵列（803,807）可以互连芯片，所以可以使芯片（605,607）更小，由此降低芯片（605,607）的成本（数量级）。

公开(公告)号：WO2008137480A3

公开(公告)日：2009-10-15

申请号：PCT/US2008062101

申请日：2008-04-30

Applicant: DSM SOLUTIONS INC ,  VORA MADHUKAR B

Inventor： VORA MADHUKAR B

IPC: H01L21/761 ,  H01L21/337 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/808

CPC classification number: H01L29/808 ,  H01L21/28525 ,  H01L21/761 ,  H01L21/76895 ,  H01L21/8213 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/1066 ,  H01L29/665 ,  H01L29/7833

Abstract: Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to isolate active areas. Insulating layer is formed on top surface of substrate and interconnect channels are etched in insulating layer which do not go down to the semiconductor substrate. Contact openings for surface contacts to wells and substrate are etched in insulating layer down to semiconductor layer. Doped silicon or metal is formed in contact openings for surface contacts and to form interconnects in channels. Silicide may be formed on top of polycrystalline silicon contacts and interconnect lines to lower resistivity. Any JFET or MOS transistor may be integrated into the resulting junction isolated active area.

Abstract translation: 用于晶体管的集成有源区隔离结构来代替更大和更昂贵的浅沟槽隔离或场氧化物来隔离晶体管。 在井之间形成PN结，并且与衬底和阱的表面接触形成多阱注入，因此施加到反向偏置PN结的偏置电压以隔离有源区。 绝缘层形成在衬底的顶表面上，互连通道被蚀刻在绝缘层中，绝缘层不会下降到半导体衬底。 用于与阱和衬底的表面接触的接触开口在绝缘层中被蚀刻到半导体层。 掺杂的硅或金属形成在用于表面接触的接触开口中并且在通道中形成互连。 可以在多晶硅触点和互连线之上形成硅化物以降低电阻率。 任何JFET或MOS晶体管可以集成到所得到的结隔离有源区域中。

公开(公告)号：WO2009079244A1

公开(公告)日：2009-06-25

申请号：PCT/US2008/085782

申请日：2008-12-08

Applicant: DSM SOLUTIONS, INC. ,  ZARKESH-HA, Payman ,  HAMLIN, Christopher, L. ,  KAPOOR, Ashok, K. ,  KOFORD, James, S. ,  VORA, Madhukar, B.

Inventor： ZARKESH-HA, Payman ,  HAMLIN, Christopher, L. ,  KAPOOR, Ashok, K. ,  KOFORD, James, S. ,  VORA, Madhukar, B.

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.

Abstract translation: 一种用于对电路进行建模的方法包括：接收网表，其定义多个电路元件之间的多个连接并识别连接的子集。 该方法还包括使用具有第一线宽度的第一组线路路由所识别的连接，并且以第二线宽度路由至少一部分剩余的连接。 第二线宽小于第一线宽度。 该方法还包括用具有第二线宽度的第三组线代替第一组线。

公开(公告)号：WO2008057814A3

公开(公告)日：2008-07-10

申请号：PCT/US2007082775

申请日：2007-10-29

Applicant: DSM SOLUTIONS INC ,  VORA MADHUKAR B

Inventor： VORA MADHUKAR B

IPC: H01L21/762 ,  H01L21/337 ,  H01L29/808

CPC classification number: H01L27/0623 ,  H01L21/02071 ,  H01L21/28525 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/8249 ,  H01L27/0922 ,  H01L27/098 ,  H01L29/66901 ,  H01L29/78

Abstract: A method of forming a semiconductor device can include forming a first layer of semiconductor material in contact with a first area of a substrate. The first area can be adjacent to at least one electrical isolation structure that extends into the substrate and has a top portion extending above a surface of the substrate. The method can also include etching, with a degree of anisotropy, the first layer to form at least a first structure in contact with the first area. Further, in a step separate from the etching step, retention of residual semiconductor material at a junction of the substrate and the at least one electrical isolation structure can be prevented.

Abstract translation: 形成半导体器件的方法可以包括形成与衬底的第一区域接触的第一半导体材料层。 第一区域可以与延伸到衬底中的至少一个电隔离结构相邻，并且具有在衬底的表面上方延伸的顶部部分。 该方法还可以包括具有一定程度的各向异性的蚀刻，第一层以形成与第一区域接触的至少第一结构。 此外，在与蚀刻步骤分离的步骤中，可以防止残留半导体材料在基板和至少一个电隔离结构的接合处的保留。

公开(公告)号：WO2008055089A3

公开(公告)日：2008-05-08

申请号：PCT/US2007/082781

申请日：2007-10-29

Applicant: DSM SOLUTIONS, INC. ,  VORA, Madhukar, B.

Inventor： VORA, Madhukar, B.

IPC: H01L27/11 ,  H01L21/8244

Abstract: The present invention relates generally to semiconductor circuits, and more particularly to semiconductor circuits having interconnected field effect transistors, methods of designing such circuits, and data structures representing such circuits.