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    SEMICONDUCTOR DEVICE WITH MAIN MEMORY UNIT AND AUXILIARY MEMORY UNIT REQUIRING PRESET OPERATION
    63.
    发明申请
    SEMICONDUCTOR DEVICE WITH MAIN MEMORY UNIT AND AUXILIARY MEMORY UNIT REQUIRING PRESET OPERATION 审中-公开
    具有主存储单元和辅助存储单元的半导体器件需要预置操作

    公开(公告)号：WO2010069076A1

    公开(公告)日：2010-06-24

    申请号：PCT/CA2009/001860

    申请日：2009-12-17

    Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  PYEON, Hong-Beom

    Inventor： PYEON, Hong-Beom

    IPC: G11C7/10 ,  G11C16/06 ,  G11C7/20 ,  G11C8/08 ,  G11C8/10

    CPC classification number: G11C11/412 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/20 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/10 ,  G11C2216/14

    Abstract: A semiconductor device for transferring input data to a non-volatile memory device. The semiconductor device comprises a virtual page buffer including a plurality of data elements; a mask buffer including a corresponding plurality of data elements; control logic circuitry for (i) setting each of the mask buffer data elements to a first logic state upon receipt of a trigger; (ii) causing input data to be written to selected virtual page buffer data elements; and (iii) causing those mask buffer data elements corresponding to the selected virtual page buffer data elements to be set to a different logic state; mask logic circuitry configured to generate masked output data by combining, for each of the virtual page buffer data elements, data read therefrom together with the logic state of the corresponding mask buffer data element; and an output interface configured to release the masked output data towards the non¬ volatile memory device.

    Abstract translation: 一种用于将输入数据传送到非易失性存储器件的半导体器件。 该半导体器件包括一个包含多个数据元素的虚拟页缓冲器; 包括对应的多个数据元素的掩码缓冲器; 控制逻辑电路，用于（i）在接收到触发时将每个掩码缓冲器数据元素设置为第一逻辑状态; （ii）使输入数据被写入所选择的虚拟页面缓冲数据元素; 和（iii）使与所选择的虚拟页面缓冲数据元素相对应的掩码缓冲器数据元素被设置为不同的逻辑状态; 掩模逻辑电路，被配置为通过将每个所述虚拟页缓冲器数据元素与对应的掩码缓冲器数据元素的逻辑状态一起组合来生成被屏蔽的输出数据; 以及输出接口，被配置为向非易失性存储器件释放被屏蔽的输出数据。

    NON-BINARY DECODER ARCHITECTURE AND CONTROL SIGNAL LOGIC FOR REDUCED CIRCUIT COMPLEXITY
    64.
    发明申请
    NON-BINARY DECODER ARCHITECTURE AND CONTROL SIGNAL LOGIC FOR REDUCED CIRCUIT COMPLEXITY 审中-公开
    非二进制解码器架构和控制信号逻辑降低电路复杂度

    公开(公告)号：WO2010053938A1

    公开(公告)日：2010-05-14

    申请号：PCT/US2009/063202

    申请日：2009-11-04

    Applicant: NEXT BIOMETRICS AS ,  TROCCOLI, Matias, N.

    Inventor： TROCCOLI, Matias, N.

    IPC: G11C8/00

    CPC classification number: H03K19/20 ,  G11C8/04 ,  G11C8/10

    Abstract: A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log 2 X inputs for receiving the clock signal inputs.

    Abstract translation: 描述了用于响应于时钟信号输入顺序启用输出的解码器，其包括与解码器的X个输出数量对应的X个逻辑级。 每个逻辑级具有多个输入，其中每个逻辑级包括少于log2X输入，用于接收时钟信号输入。

    ROW MASK ADDRESSING
    65.
    发明申请
    ROW MASK ADDRESSING 审中-公开
    ROW MASK寻址

    公开(公告)号：WO2010016879A1

    公开(公告)日：2010-02-11

    申请号：PCT/US2009/004443

    申请日：2009-08-03

    Applicant: MICRON TECHNOLOGY, INC. ,  MANNING, Troy, A.

    Inventor： MANNING, Troy, A.

    IPC: G11C8/00 ,  G11C8/10 ,  G11C8/18 ,  G11C8/08

    CPC classification number: G11C8/10 ,  G11C11/4087

    Abstract: Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed.

    Abstract translation: 电子设备，系统和方法可以操作结构以访问存储器阵列的行的一部分而不访问整个行。 公开了附加装置，系统和方法。

    NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS
    66.
    发明申请
    NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS 审中-公开
    非易失性存储器，带有通道和扩展源/漏区

    公开(公告)号：WO2009129053A1

    公开(公告)日：2009-10-22

    申请号：PCT/US2009/039202

    申请日：2009-04-01

    Applicant: SANDISK CORPORATION ,  CHIEN, Henry ,  PURAYATH, Vinod, R. ,  KAI, James ,  MATAMIS, George ,  ORIMOTO, Takashi

    Inventor： CHIEN, Henry ,  PURAYATH, Vinod, R. ,  KAI, James ,  MATAMIS, George ,  ORIMOTO, Takashi

    IPC: G11C11/56 ,  G11C11/16

    CPC classification number: G11C8/10 ,  G11C8/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C19/00 ,  H01L21/28273 ,  H01L27/11521

    Abstract: A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

    Abstract translation: 一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。 在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。 浮动门可以具有均匀的宽度或倒T形。 凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为 降低。 侧壁绝缘层与底部绝缘层的厚度的比可以为约0.3〜0.67。

    MEMORY DEVICE WITH SELF-REFRESH OPERATIONS
    67.
    发明申请
    MEMORY DEVICE WITH SELF-REFRESH OPERATIONS 审中-公开
    具有自我修复操作的存储设备

    公开(公告)号：WO2009076511A2

    公开(公告)日：2009-06-18

    申请号：PCT/US2008086387

    申请日：2008-12-11

    Applicant: ZMOS TECHNOLOGY INC ,  CHOI MYUNG CHAN ,  YOO SEUNG-MOON ,  KWON ARTHUR

    Inventor： CHOI MYUNG CHAN ,  YOO SEUNG-MOON ,  KWON ARTHUR

    IPC: G11C11/401 ,  G11C11/40

    CPC classification number: G11C11/406 ,  G11C8/10 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4065

    Abstract: An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh.

    Abstract translation: 一种用于在具有内部自刷新电路的动态存储器件中降低功耗的装置和方法。 用于产生隔离器控制（ISO），预解码行地址（PXID）和/或字使能（WE）信号的电路被配置为响应于接收到自刷新和刷新计数器信号，以在自身中输出不同的定时和排序 -refresh模式比在正常模式下的存储设备。 传统上，ISO信号由也可以控制位线均衡（BLEQ）和读出放大器使能（SAPN）的块选择电路控制。 而在常规电路中，PXID和WE信号是响应于地址解码器的输出产生的，因此与地址解码器的输出有固定的时序。 使用不同的定时和排序可以降低功耗，例如在自刷新期间通过在每个块输出更少的信号转换。

    MEMORY STRUCTURE WITH WORD LINE BUFFERS
    69.
    发明申请
    MEMORY STRUCTURE WITH WORD LINE BUFFERS 审中-公开
    内存结构与字线缓冲区

    公开(公告)号：WO2008150844A1

    公开(公告)日：2008-12-11

    申请号：PCT/US2008065050

    申请日：2008-05-29

    Applicant: MARVELL WORLD TRADE LTD ,  SUTARDJA PANTAS

    Inventor： SUTARDJA PANTAS

    IPC: G11C8/08 ,  G11C8/10 ,  G11C11/408

    CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C11/4085

    Abstract: A memory comprises a plurality of memory cells. A row decoder module selectively drives word lines using a voltage level to access selected ones of the memory cells. A first regeneration module selectively pulls the voltage level on one of the word lines to one of first and second predetermined voltage levels. At least one of the memory cells of the one of the word lines is located between the first regeneration module and the row decoder module.

    Abstract translation: 存储器包括多个存储单元。 行解码器模块使用电压电平选择性地驱动字线以访问所选存储单元。 第一再生模块有选择地将一条字线上的电压电平拉到第一和第二预定电压电平之一。 一条字线的至少一个存储单元位于第一再生模块和行解码器模块之间。

    MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM
    70.
    发明申请
    MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM 审中-公开
    用于存储器和存储器系统的模块化命令结构

    公开(公告)号：WO2008022434A1

    公开(公告)日：2008-02-28

    申请号：PCT/CA2007/001428

    申请日：2007-08-20

    Applicant: MOSAID TECHNOLOGIES INCORPORATED

    Inventor： KIM, Jin-Ki ,  OH, HakJune ,  PYEON, Hong Beom

    IPC: G11C8/00 ,  G06F12/02 ,  G06F13/14 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12

    CPC classification number: G06F13/4243 ,  G11C7/10 ,  G11C7/1042 ,  G11C7/20 ,  G11C8/06 ,  G11C8/10

    Abstract: A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

    Abstract translation: 包括存储器系统和存储器控制器的系统连接到主机系统。 存储器系统具有存储数据的至少一个存储器件。 控制器将来自主机系统的请求转换成由至少一个存储设备可解释的一个或多个可分离命令。 每个命令具有模块化结构，其包括用于至少一个存储器设备中的一个的地址标识符和表示由至少一个存储器设备之一执行的操作的命令标识符。 至少一个存储器设备和控制器处于用于通信的串联连接配置中，使得仅一个存储器设备与控制器通信以输入到存储器系统中。 存储器系统可以包括连接到公共总线的多个存储器件。

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