公开(公告)号：WO2013074178A1

公开(公告)日：2013-05-23

申请号：PCT/US2012/052749

申请日：2012-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  QUESTAD, David, L. ,  SAUTER, Wolfgang ,  SULLIVAN, Timothy, D.

Inventor： DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  QUESTAD, David, L. ,  SAUTER, Wolfgang ,  SULLIVAN, Timothy, D.

IPC: H01L23/48

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02126 ,  H01L2224/02235 ,  H01L2224/0401 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06131 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/1312 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012

Abstract: A topographical feature (305) is formed proximate to a conductive bond pad (235) that is used to couple a solder bump (160) to a semiconductor die (140). The topographical feature (305) is separated from the conductive bond pad (235) by a gap (310). In one embodiment, the topographical feature (305) is formed at a location that is slightly beyond the perimeter of the solder bump (160), wherein an edge of the bump (160) is aligned vertically to coincide with the gap (310) separating the conductive bond pad (235) from the topographical feature (305). The topographical feature (305) provides thickness enhancement of a non-conductive layer (240) disposed over the semiconductor die (140) and the conductive bond pad (235) and stress buffering.

Abstract translation: 形成靠近用于将焊料凸块（160）耦合到半导体管芯（140）的导电接合焊盘（235）的形貌特征（305）。 地形特征（305）通过间隙（310）与导电接合垫（235）分离。 在一个实施例中，形貌特征（305）形成在稍微超过焊料凸块（160）的周边的位置处，其中凸起（160）的边缘垂直对准，以与间隔（310）分离重合 来自所述形貌特征（305）的所述导电接合焊盘（235）。 形貌特征（305）提供设置在半导体管芯（140）和导电接合焊盘（235）之上的非导电层（240）的厚度增强和应力缓冲。

公开(公告)号：WO2012010420A1

公开(公告)日：2012-01-26

申请号：PCT/EP2011/061430

申请日：2011-07-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  COONEY III, Edward, Crandal ,  MUSANTE, Charles, Francis ,  LEIDY, Robert, Kenneth ,  GAMBINO, Jeffrey ,  TWOMBLY, John

Inventor： COONEY III, Edward, Crandal ,  MUSANTE, Charles, Francis ,  LEIDY, Robert, Kenneth ,  GAMBINO, Jeffrey ,  TWOMBLY, John

IPC: H01L27/146 ,  C23C16/40

CPC classification number: H01L31/02325 ,  C23C16/02 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/505 ,  G06F17/5045 ,  H01L27/14627 ,  H01L27/14685

Abstract: Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.

Abstract translation: 公开了用于改善成像器微透镜结构的保护层的附着力的方法，结构和设计结构。 制造半导体结构的方法包括在微透镜和保护氧化物层之间形成界面区域。 界面区域的氧浓度低于保护氧化物层。

公开(公告)号：WO2010134922A1

公开(公告)日：2010-11-25

申请号：PCT/US2009/044952

申请日：2009-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FILIPPI, Ronald ,  STANDAERT, Theodorus, E. ,  GRUNOW, Stephan ,  SANKARAN, Sujatha ,  CHANDA, Kaushik ,  GAMBINO, Jeffrey, P. ,  SIMON, Andrew, H. ,  HU, Chao-kun ,  BONILLA, Griselda

Inventor： FILIPPI, Ronald ,  STANDAERT, Theodorus, E. ,  GRUNOW, Stephan ,  SANKARAN, Sujatha ,  CHANDA, Kaushik ,  GAMBINO, Jeffrey, P. ,  SIMON, Andrew, H. ,  HU, Chao-kun ,  BONILLA, Griselda

IPC: H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse structure for an integrated circuit device includes an elongated metal interconnect layer (106) defined within an insulating layer; a metal cap layer (108) formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer (112) formed on both the metal cap layer (108) and the remaining portions of the metal interconnect layer not having the metal cap layer (108) formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer (108) formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer (106).

Abstract translation: 用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层（106）; 金属盖层（108），仅形成在金属互连层的顶表面的一部分上; 以及形成在所述金属覆盖层（108）和所述金属互连层的不具有形成在其上的金属覆盖层（108）的其余部分的电介质盖层（112） 其中不具有形成在其上的金属覆盖层（108）的金属互连层的其余部分容易受到电迁移故障机制的影响，以便于通过施加通过细长金属互连层（106）的电流来编程熔丝结构， 。

公开(公告)号：WO2009149222A1

公开(公告)日：2009-12-10

申请号：PCT/US2009/046189

申请日：2009-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  JAFFE, Mark, D. ,  GAMBINO, Jeffrey, P. ,  LEIDY, Robert, K. ,  MUSANTE, Charles, F. ,  RASSEL, Richard, J.

Inventor： JAFFE, Mark, D. ,  GAMBINO, Jeffrey, P. ,  LEIDY, Robert, K. ,  MUSANTE, Charles, F. ,  RASSEL, Richard, J.

IPC: H01L27/00

CPC classification number: H01L27/14627 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14636

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer (22) with respect to a planarizing layer (18) within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer (20') of different dimensions than active lens layer (20) located over a circuitry portion (Rl) of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture (A) within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion (Rl) within the particular image sensor structures.

Abstract translation: 多个图像传感器结构和用于制造多个图像传感器结构的多种方法提供了相对于多个图像传感器结构内的平坦化层（18）抑制的透镜封盖层（22）的开裂和分层。 特定的图像传感器结构和相关方法包括与位于特定图像传感器结构内的衬底的电路部分（R1）之上的有源透镜层（20）不同的至少一个虚拟透镜层（20'）。 附加的特定图像传感器结构包括平坦化层内的孔径（A）和位于特定图像传感器结构内的电路部分（R1）上的平坦化层的倾斜端壁中的至少一个。

公开(公告)号：WO2008061865A1

公开(公告)日：2008-05-29

申请号：PCT/EP2007/061766

申请日：2007-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  DAUBENSPECK, Timothy, Harrison ,  SAUTER, Wolfgang ,  GAMBINO, Jeffrey, Peter ,  MUZZY, Christopher, David

Inventor： DAUBENSPECK, Timothy, Harrison ,  SAUTER, Wolfgang ,  GAMBINO, Jeffrey, Peter ,  MUZZY, Christopher, David

IPC: B23K1/20 ,  B23K20/24 ,  H01L25/065

CPC classification number: B23K1/20 ,  B23K1/0016 ,  B23K20/004 ,  B23K20/24 ,  B23K2201/40 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/85011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region (102) for the wire bond and a solder bond metal region (104) for the solder bond; forming a protective layer (250) over the wire bond metal region only; forming a silicon nitride layer (106) over a silicon oxide layer (108) over the wire bond metal region and the solder bond metal region,- forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.

Abstract translation: 公开了形成线和焊接结合结构的方法。 在一个实施例中，一种方法包括提供一种结构，其包括用于引线键合的引线键合金属区域（102）和用于焊点的焊接接合金属区域（104） 仅在引线键合金属区域上形成保护层（250）; 在所述引线接合金属区域和所述焊接金属区域上方的氧化硅层（108）上形成氮化硅层（106）， - 在保持所述引线接合金属区域的同时，形成所述焊料接合到所述焊料接合金属区域; 使引线接合金属区域露出，包括去除保护层; 并且将线接合形成到引线接合金属区域。 如果需要，可以在单个多部件晶片（MPW）晶片上或单个芯片上使引线键合和焊接结合结构可访问。

公开(公告)号：WO2006071540A2

公开(公告)日：2006-07-06

申请号：PCT/US2005/045328

申请日：2005-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ADKISSON, James, W. ,  GAMBINO, Jeffrey, P. ,  JAFFE, Mark, D. ,  LEIDY, Robert, K. ,  RASSEL, Richard, J. ,  STAMPER, Anthony, K.

Inventor： ADKISSON, James, W. ,  GAMBINO, Jeffrey, P. ,  JAFFE, Mark, D. ,  LEIDY, Robert, K. ,  RASSEL, Richard, J. ,  STAMPER, Anthony, K.

IPC: H01L31/113 ,  H01L31/0232 ,  H01L31/00

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

Abstract: An image sensor (20) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (135a, 135b) allowing for incorporation of a thinner interlevel dielectric stack (130a-130c) to result in a pixel array (100) exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal (132a, 132b) that traverses the optical path of each pixel in the sensor array or, that have portions (50) of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer (142) may be formed atop the Cu metallization by a self-aligned deposition.

Abstract translation: 一种图像传感器（20）及其制造方法，其中传感器包括铜（Cu）金属化水平（135a，135b），允许掺入更薄的层间电介质堆叠（130a-130c）以产生呈现增加的像素阵列（100） 光敏感。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属（132a，132b）的最小厚度的结构，或者具有从每个的光路中选择性地去除的阻挡层金属的部分（50） 像素，从而使反射率最小化。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层（142）可以通过自对准沉积形成在Cu金属化顶上。

公开(公告)号：WO2013012544A1

公开(公告)日：2013-01-24

申请号：PCT/US2012/044908

申请日：2012-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ADKISSON, James, W. ,  CANDRA, Panglijen ,  DUNBAR, Thomas, J. ,  GAMBINO, Jeffrey, P. ,  JAFFE, Mark, D. ,  STAMPER, Anthony, K. ,  WOLF, Randy, L.

Inventor： ADKISSON, James, W. ,  CANDRA, Panglijen ,  DUNBAR, Thomas, J. ,  GAMBINO, Jeffrey, P. ,  JAFFE, Mark, D. ,  STAMPER, Anthony, K. ,  WOLF, Randy, L.

IPC: H03H9/64

CPC classification number: H03H9/14538 ,  H03H3/08

Abstract: Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate (110; Fig 3); a planar barrier layer (120) disposed above the piezoelectric substrate, and at least one conductor buried (130) in the piezoelectric substrate and the planar barrier layer.

Abstract translation: 本文公开了一种表面声波（SAW）滤波器及其制造方法。 SAW滤波器包括压电基片（110;图3）; 设置在所述压电基板上方的平面阻挡层（120），以及在所述压电基板和所述平面阻挡层中埋设的至少一个导体（130）。

公开(公告)号：WO2011163429A2

公开(公告)日：2011-12-29

申请号：PCT/US2011/041546

申请日：2011-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GAMBINO, Jeffrey, P. ,  MOON, Matthew, D. ,  MURPHY, William, J. ,  NAKOS, James, S. ,  PASTEL, Paul, W. ,  PHILIPS, Brett, A.

Inventor： GAMBINO, Jeffrey, P. ,  MOON, Matthew, D. ,  MURPHY, William, J. ,  NAKOS, James, S. ,  PASTEL, Paul, W. ,  PHILIPS, Brett, A.

IPC: H01L21/02

CPC classification number: H01L28/55 ,  H01L27/11507

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator (18) layer of a CMOS structure (10). The method further includes forming a top plate (32) and a bottom plate (28) over the barrier layer. The method further includes forming a ferro-electric material (30) between the top plate (32) and the bottom plate (28). The method further includes encapsulating the barrier layer, top plate (32), bottom plate (28) and ferro-electric material (30) with an encapsulating material (36). The method further includes forming contacts (20) to the top plate (32) and bottom plate (28), through the encapsulating material (36). At least the contact (20) to the top plate (32) and a contact (20) to a diffusion of the CMOS structure are in electrical connection through a common wire.

Abstract translation: 铁电电容器模块，制造方法和设计结构。 制造铁电电容器的方法包括在CMOS结构（10）的绝缘体（18）层上形成阻挡层。 该方法还包括在阻挡层上形成顶板（32）和底板（28）。 该方法还包括在顶板（32）和底板（28）之间形成铁电材料（30）。 该方法还包括用封装材料（36）封装阻挡层，顶板（32），底板（28）和铁电材料（30）。 该方法还包括通过封装材料（36）将接触件（20）形成到顶板（32）和底板（28）。 至少到达顶板（32）的触点（20）和与CMOS结构的扩散的触点（20）通过公共导线电连接。

公开(公告)号：WO2009140099A3

公开(公告)日：2010-01-21

申请号：PCT/US2009042766

申请日：2009-05-05

Applicant: IBM ,  ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

Inventor： ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

IPC: H01L31/112

CPC classification number: H01L27/14685 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14689 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

Abstract translation: 具有小于由光电二极管（8）可检测的光的波长范围的垂直（h）和横向（p）尺寸的凸起（5）形成在具有不同折射率的两个层之间的光学界面处。 突起可以通过使用在第二聚合物嵌段组分（111）的基体内形成第一聚合物嵌段组分（112）的亚光刻特征阵列的自组装嵌段共聚物来形成。 聚合物嵌段组分的图案被转移到第一光学层（4）中以形成纳米级突起的阵列。 或者，可以使用常规光刻来形成尺寸小于光的波长的突起。 第二光学层直接形成在第一光学层的突起上。 第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

公开(公告)号：WO2008058847A1

公开(公告)日：2008-05-22

申请号：PCT/EP2007/061705

申请日：2007-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  GAMBINO, Jeffrey, Peter ,  ADKISSON, James, William ,  SPROGIS, Edmund, Juris ,  RASSEL, Richard, John ,  LEIDY, Robert, Kenneth ,  JAFFE, Mark, David ,  LUCE, Stephen, Ellinwood ,  HE, Zhong-Xiang

Inventor： GAMBINO, Jeffrey, Peter ,  ADKISSON, James, William ,  SPROGIS, Edmund, Juris ,  RASSEL, Richard, John ,  LEIDY, Robert, Kenneth ,  JAFFE, Mark, David ,  LUCE, Stephen, Ellinwood ,  HE, Zhong-Xiang

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2924/00014

Abstract: A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein "m" levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having "n" levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.

Abstract translation: CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个层形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。 具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。 微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。