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1.3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD 审中-公开
Title translation: 具有特征和方法的3-D半导体结构公开(公告)号:WO2009085609A2
公开(公告)日:2009-07-09
申请号:PCT/US2008086174
申请日:2008-12-10
Applicant: FREESCALE SEMICONDUCTOR INC , POZDER SCOTT K , CHATTERJEE RITWIK
Inventor: POZDER SCOTT K , CHATTERJEE RITWIK
CPC classification number: H01L24/13 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/06102 , H01L2224/10135 , H01L2224/10165 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14517 , H01L2224/16 , H01L2224/16503 , H01L2224/81136 , H01L2224/81141 , H01L2224/81801 , H01L2224/83365 , H01L2224/83385 , H01L2225/06513 , H01L2924/00013 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/00014 , H01L2224/13099 , H01L2924/01007
Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.
Abstract translation: 模具上的模具组件具有第一模具(10)和第二模具(50)。 第一模具(10)具有延伸第一模具上方的第一高度的第一接触延伸部(28,42)和钉(32,44,45)。 第二模具(50)具有连接到第一接触延伸部的第二接触延伸部(68),并且具有延伸在围绕钉的第二模具上方的第二高度的容纳特征(62)。 钉子延伸穿过包含的特征。 因为钉延伸穿过容纳特征,所以第一和第二管芯之间的横向移动可以导致钉与接合特征接触并被约束。 因此,钉和容纳特征可用于约束第一和第二管芯之间的运动。
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2.TECHNIQUE FOR EFFICIENTLY PATTERNING AN UNDERBUMP METALLIZATION LAYER USING A DRY ETCH PROCESS 审中-公开
Title translation: 使用干蚀刻工艺有效地绘制下层金属化层的技术公开(公告)号:WO2007015938A2
公开(公告)日:2007-02-08
申请号:PCT/US2006/028194
申请日:2006-07-20
Applicant: ADVANCED MICRO DEVICES, INC. , KUECHENMEISTER, Frank , PLATZ, Alexander , JUNGNICKEL, Gotthard , SIURY, Kerstin
Inventor: KUECHENMEISTER, Frank , PLATZ, Alexander , JUNGNICKEL, Gotthard , SIURY, Kerstin
IPC: H01L21/60 , H01L23/485 , H05K3/34 , H01L21/3213 , C25F3/02
CPC classification number: H01L24/05 , H01L21/02071 , H01L21/32134 , H01L24/03 , H01L24/11 , H01L24/12 , H01L24/13 , H01L2224/0361 , H01L2224/0381 , H01L2224/03901 , H01L2224/03912 , H01L2224/0401 , H01L2224/05582 , H01L2224/05647 , H01L2224/05671 , H01L2224/11849 , H01L2224/11912 , H01L2224/13099 , H01L2224/131 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
Abstract: By patterning an underbump metallization layer stack (105) on the basis of a dry etch process (111), significant advantages may be achieved compared to conventional techniques involving a highly complex wet chemical etch process. In particular embodiments, a titanium tungsten layer or any other appropriate last layer (105B) of an underbump metallization layer stack (105) may be etched on the basis of a plasma etch process (107) using a fluorine-based chemistry and oxygen as a physical component. Moreover, appropriate cleaning processes (110, 113) may be performed for removing particles (109) and residues (112) prior to and after the plasma-based patterning process (107).
Abstract translation: 通过基于干法蚀刻工艺(111)图案化底部金属化层堆叠(105),与涉及高度复杂的湿化学蚀刻工艺的常规技术相比,可以实现显着的优点。 在特定实施例中,可以基于等离子体蚀刻工艺(107),使用氟基化学和氧气作为蚀刻方法来蚀刻钛钨层或下掺杂金属化层堆叠(105)的任何其它合适的最后层(105B) 物理成分。 此外,可以在等离子体图案化工艺(107)之前和之后进行适当的清洁过程(110,113)以去除颗粒(109)和残余物(112)。
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3.METHODS OF FORMING SOLDER BUMPS ON EXPOSED METAL PADS AND RELATED STRUCTURES 审中-公开
Title translation: 在暴露的金属垫片和相关结构上形成焊膏的方法公开(公告)号:WO2005101499A2
公开(公告)日:2005-10-27
申请号:PCT/US2005/012029
申请日:2005-04-12
Applicant: UNITIVE INTERNATIONAL LIMITED , MIS, J. Daniel
Inventor: MIS, J. Daniel
IPC: H01L23/48
CPC classification number: H01L24/05 , H01L24/03 , H01L24/11 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05 , H01L2224/05562 , H01L2224/05564 , H01L2224/05568 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/1147 , H01L2224/13007 , H01L2224/13021 , H01L2224/13023 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2224/05552
Abstract: A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrier layer. In addition, an interconnection structure may be provided on the conductive barrier layer with the conductive barrier layer being between the interconnection structure and the metal pad. Moreover, the interconnection structure and the conductive barrier layer may include different materials. Related structures are also discussed.
Abstract translation: 形成电子结构的方法可以包括提供其上具有金属垫的基板。 可以在金属焊盘的第一部分上形成导电阻挡层,并且金属焊盘的第二暴露部分可以没有导电阻挡层。 此外,可以在导电阻挡层上提供互连结构,其中导电阻挡层位于互连结构和金属焊盘之间。 此外,互连结构和导电阻挡层可以包括不同的材料。 还讨论了相关结构。
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公开(公告)号:WO2015020856A1
公开(公告)日:2015-02-12
申请号:PCT/US2014/048945
申请日:2014-07-30
Applicant: QUALCOMM INCORPORATED
Inventor: HAU-RIEGE, Christine Sung-An , YAU, You-Wen , CAFFEY, Kevin, Patrick , KESER, Lizabeth, Ann , MCALLISTER, Gene, H. , ALVARADO, Reynante, Tamunan , BEZUK, Steve, J. , GASTELUM, Damion, Bryan
IPC: H01L23/532
CPC classification number: H01L23/485 , H01L21/76841 , H01L21/76895 , H01L23/525 , H01L23/53238 , H01L23/53266 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02331 , H01L2224/0239 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05022 , H01L2224/05024 , H01L2224/05083 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05548 , H01L2224/05572 , H01L2224/05582 , H01L2224/05583 , H01L2224/05647 , H01L2224/05657 , H01L2224/1134 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/94 , H01L2924/01074 , H01L2924/00014 , H01L2224/03 , H01L2224/11 , H01L2924/014
Abstract: Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.
Abstract translation: 一些实施方案提供了一种半导体器件(例如,管芯),其包括衬底,耦合到衬底的几个金属层和电介质层,耦合到多个金属层中的一个的焊盘,耦合到衬垫的第一金属再分布层,以及 耦合到第一金属再分配层的第二金属再分配层。 第二金属再分布层包括钴钨磷材料。 在一些实施方案中,第一金属再分配层是铜层。 在一些实施方案中,半导体器件还包括第一底部浸渍金属化(UBM)层和第二底部金属化(UBM)层。
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公开(公告)号:WO2014033977A1
公开(公告)日:2014-03-06
申请号:PCT/JP2013/001915
申请日:2013-03-21
Applicant: パナソニック株式会社
Inventor: 樋口 裕一
IPC: H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC classification number: H01L25/0657 , H01L21/563 , H01L23/481 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/02372 , H01L2224/0239 , H01L2224/0345 , H01L2224/03462 , H01L2224/03614 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05011 , H01L2224/05012 , H01L2224/05015 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05166 , H01L2224/05187 , H01L2224/05551 , H01L2224/05552 , H01L2224/05555 , H01L2224/05557 , H01L2224/05558 , H01L2224/05559 , H01L2224/05573 , H01L2224/05582 , H01L2224/05609 , H01L2224/05611 , H01L2224/05613 , H01L2224/05617 , H01L2224/05618 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05666 , H01L2224/05684 , H01L2224/1145 , H01L2224/11462 , H01L2224/13014 , H01L2224/13017 , H01L2224/13019 , H01L2224/13024 , H01L2224/13025 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13117 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13166 , H01L2224/13184 , H01L2224/16014 , H01L2224/16058 , H01L2224/16148 , H01L2224/16237 , H01L2224/32145 , H01L2224/73104 , H01L2224/73204 , H01L2224/8112 , H01L2224/81121 , H01L2224/8114 , H01L2224/81141 , H01L2224/81143 , H01L2224/81193 , H01L2224/81201 , H01L2224/83862 , H01L2224/92125 , H01L2225/06513 , H01L2225/06541 , H01L2225/06548 , H01L2225/06593 , H01L2924/01032 , H01L2924/207 , H01L2924/2075 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/381 , H01L2924/384 , H01L2224/16225 , H01L2224/32225 , H01L2924/00012 , H01L2924/00014 , H01L2924/04953 , H01L2924/014 , H01L2924/01022 , H01L2924/01029
Abstract: 第1の半導体チップ(100)と第2の半導体チップ(200)とが接合された積層チップを有する半導体装置である。第1の半導体チップの主面上には、第1の電極パッド(110)と、第1の電極パッドの上に形成された第1のバンプ(120)とが形成されている。第2の半導体チップ(200)の主面上には、第1のバンプと接合するように第2のバンプ(220)が形成されている。第1の電極パッド(110)は、中央に段差状となる開口部を有している。第1のバンプ(120)は、第1の電極パッド(110)における開口部とその周辺部との段差状に跨るように形成された中央が窪んだ凹状を有する。
Abstract translation: 该半导体器件具有通过接合第一半导体芯片(100)和第二半导体芯片(200)而产生的层叠芯片。 在第一半导体芯片的主表面上形成有形成在第一电极焊盘上的第一电极焊盘(110)和第一凸块(120)。 在第二半导体芯片(200)的主表面上形成有用于与第一凸块接合的第二凸块(220)。 第一电极焊盘(110)具有孔,使得中心部分具有阶梯形状。 第一凸块(120)具有中心部分凹陷的凹陷形状,以便跨越第一电极焊盘(110)的孔径和周边部分的阶梯形状。
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公开(公告)号:WO2010089814A1
公开(公告)日:2010-08-12
申请号:PCT/JP2009/003722
申请日:2009-08-04
Applicant: パナソニック株式会社 , 仲野純章
Inventor: 仲野純章
IPC: H01L21/60
CPC classification number: H01L24/11 , H01L23/3171 , H01L24/05 , H01L24/13 , H01L2224/03828 , H01L2224/0401 , H01L2224/05073 , H01L2224/05124 , H01L2224/05568 , H01L2224/05571 , H01L2224/05573 , H01L2224/05582 , H01L2224/05644 , H01L2224/05655 , H01L2224/11334 , H01L2224/1148 , H01L2224/11849 , H01L2224/13021 , H01L2224/13023 , H01L2224/13111 , H01L2224/81024 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/3841 , H01L2224/05552
Abstract: 本発明は、印刷されるフラックスの過度な広がりを防止出来る半導体基板構造に関する。半導体基板構造は、半導体基板本体(100)の上に形成された電極パッド(103)と、半導体基板本体(100)の上に電極パッド(103)と間隔をおいて形成された保護膜(123)と、電極パッド(103)の上に形成されたバンプ(111)とを備えている。保護膜(123)は、電極パッド(103)を囲む障壁部(123a)を有している。障壁部(123a)は、保護膜(123)における障壁部(123a)を除く部分と高さが異なっている。
Abstract translation: 提供了可以消除要印刷的焊剂的过度扩散的半导体衬底结构。 半导体衬底结构设置有形成在半导体衬底主体(100)上的电极焊盘(103)。 通过与所述电极焊盘(103)间隔开而形成在所述半导体衬底主体(100)上的保护膜(123); 以及形成在所述电极焊盘(103)上的凸块(111)。 保护膜(123)具有围绕电极焊盘(103)的阻挡部(123a)。 阻挡部(123a)的高度不同于保护膜(123)上的阻挡部(123a)以外的部分的高度。
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7.METHODS OF FORMING SOLDER BUMPS ON EXPOSED METAL PADS AND RELATED STRUCTURES 审中-公开
Title translation: 在暴露的金属垫片和相关结构上形成焊膏的方法公开(公告)号:WO2005101499A3
公开(公告)日:2006-01-05
申请号:PCT/US2005012029
申请日:2005-04-12
Applicant: UNITIVE INT LTD , MIS J DANIEL
Inventor: MIS J DANIEL
IPC: H01L21/60 , H01L23/485
CPC classification number: H01L24/05 , H01L24/03 , H01L24/11 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05 , H01L2224/05562 , H01L2224/05564 , H01L2224/05568 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/1147 , H01L2224/13007 , H01L2224/13021 , H01L2224/13023 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2224/05552
Abstract: A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrier layer. In addition, an interconnection structure may be provided on the conductive barrier layer with the conductive barrier layer being between the interconnection structure and the metal pad. Moreover, the interconnection structure and the conductive barrier layer may include different materials. Related structures are also discussed.
Abstract translation: 形成电子结构的方法可以包括提供其上具有金属垫的基板。 可以在金属焊盘的第一部分上形成导电阻挡层,并且金属焊盘的第二暴露部分可以没有导电阻挡层。 此外,可以在导电阻挡层上提供互连结构,其中导电阻挡层位于互连结构和金属焊盘之间。 此外,互连结构和导电阻挡层可以包括不同的材料。 还讨论了相关结构。
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8.PROCEDE D'ASSEMBLAGE DE DEUX COMPOSANTS ELECTRONIQUES, DE TYPE FLIP-CHIP PAR RECUIT UV, ASSEMBLAGE OBTENU 审中-公开
Title translation: 通过紫外线退火和组装获得的两种电子元件的片状芯片组装方法公开(公告)号:WO2015001484A1
公开(公告)日:2015-01-08
申请号:PCT/IB2014/062767
申请日:2014-07-01
Inventor: ALIANE, Abdelkader , REVAUX, Amélie
IPC: H01L23/485 , H01L29/06 , H01L21/60
CPC classification number: H01L24/73 , H01L21/4853 , H01L21/4867 , H01L23/4985 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/0345 , H01L2224/0361 , H01L2224/0391 , H01L2224/0401 , H01L2224/05017 , H01L2224/05018 , H01L2224/05026 , H01L2224/05082 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05169 , H01L2224/05541 , H01L2224/05557 , H01L2224/05558 , H01L2224/05571 , H01L2224/05573 , H01L2224/05582 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/05669 , H01L2224/1147 , H01L2224/13005 , H01L2224/13021 , H01L2224/13026 , H01L2224/13109 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/29147 , H01L2224/73204 , H01L2224/75253 , H01L2224/81048 , H01L2224/81125 , H01L2224/81191 , H01L2224/8122 , H01L2224/81224 , H01L2224/8123 , H01L2224/81365 , H01L2224/81395 , H01L2224/81444 , H01L2224/81455 , H01L2224/81466 , H01L2224/81486 , H01L2224/81815 , H01L2224/83125 , H01L2224/83192 , H01L2224/8322 , H01L2224/8323 , H01L2224/92225 , H01L2924/00014 , H01L2924/014 , H01L2924/0541 , H01L2924/00012 , H01L2924/206 , H01L2924/01029 , H01L2924/0105 , H01L2224/05552
Abstract: L'invention concerne un procédé d'assemblage de type Flip-Chip, entre un premier (1) et un deuxième (2) composants comportant chacun des plots de connexion (11, 21) sur une de leurs faces, dites faces d'assemblage, selon lequel on reporte les composants l'un sur l'autre par leurs faces d'assemblage de sorte à réaliser des interconnexions électriques entre les plots du premier et ceux du deuxième composant. Selon l'invention, on réalise une transformation de l'oxyde de cuivre en cuivre par recuit UV, très localement dans l'espacement entre composants au moins autour des zones au droit des plots de connexion. Le procédé selon l'invention peut être utilisé pour n'importe quel composant transparent aux UV, y compris pour des substrats en matière plastique tels que des substrats en PEN ou en PET. L'invention concerne également l'assemblage entre deux composants obtenu par le procédé.
Abstract translation: 本发明涉及一种在第一(1)和第二(2)部件之间倒装芯片组装的方法,每个部件包括在相同的一个表面上的连接焊盘(11,21),其被称为组装面,其涉及将部件转移到 彼此经由其组装面,以便在第一和第二部件的焊盘之间产生电互连。 本发明涉及通过在组件之间的间隙中非常局部地至少在与连接焊盘相邻的区域的周围进行UV退火来将氧化铜转化为铜。 根据本发明的方法可用于对紫外线透明的任何组件,包括由诸如由PEN或PET制成的基材的塑料材料制成的基材。 本发明还涉及通过该方法获得的两种组分的组装。
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公开(公告)号:WO2013157064A1
公开(公告)日:2013-10-24
申请号:PCT/JP2012/060218
申请日:2012-04-16
Inventor: 谷黒 克守
CPC classification number: B23K3/0607 , B23K1/0016 , B23K1/08 , B23K1/20 , B23K1/203 , B23K3/0646 , B23K3/0669 , B23K3/082 , B23K35/262 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/741 , H01L24/742 , H01L2224/03312 , H01L2224/03418 , H01L2224/036 , H01L2224/0381 , H01L2224/03821 , H01L2224/0401 , H01L2224/05073 , H01L2224/05082 , H01L2224/05111 , H01L2224/05147 , H01L2224/05582 , H01L2224/05611 , H01L2224/05647 , H01L2224/0569 , H01L2224/11312 , H01L2224/116 , H01L2224/11821 , H01L2224/13111 , H01L2224/1369 , H01L2224/741 , H01L2924/381 , H05K3/0085 , H05K3/282 , H05K3/3468 , H05K2203/081 , H05K2203/122 , H05K2203/1366 , H05K2203/1518 , Y10T428/31678 , H01L2224/1141 , H01L2924/00012 , H01L2924/00014 , H01L2924/01028 , H01L2924/01047 , H01L2924/01029 , H01L2924/01032 , H01L2924/01083 , H01L2924/0103 , H01L2924/01051 , H01L2224/03
Abstract: 銅電極(2)を有する被処理部材(10)を有機脂肪酸含有溶液(31)に浸漬し、浸漬した被処理部材(10)を有機脂肪酸含有溶液(31)中で水平移動する第1処理部と、処理した被処理部材(10)を上方向の蒸気雰囲気の空間部(24)に引き上げながら、被処理部材(10)に向けて溶融はんだ(5a)の噴流(5')を吹き付ける噴射手段(33)を備えた第2処理部と、処理した被処理部材(10)を空間部(24)中で水平移動した後に有機脂肪酸含有溶(31)液中に降下させながら、被処理部材(10)上の余剰の溶融はんだ(5a)に有機脂肪酸含有溶液(31)を吹き付けて除去する噴射手段(34)を備えた第3処理部と、処理した被処理部材(10)を有機脂肪酸含有溶液(31)中で水平移動した後に上方向に引き上げて溶液外に取り出す第4処理部とを備えるはんだ付け装置により低コストで、歩留まりが高く、信頼性の高いはんだ付けを行う。
Abstract translation: 低成本,高产出和高可靠性的焊接是通过一种焊接装置进行的,所述焊接装置具有:将具有铜电极(2)的待处理部件(10)浸渍在含有机脂肪酸的溶液中的第一处理单元 (31)并将待处理的浸渍构件(10)水平移动到含有机脂肪酸溶液(31)中; 第二处理单元,其设置有喷射装置,用于在待处理的待处理构件(10)被向上升到空气部分(24)的同时,喷射熔融的喷射流(5'), 焊料(5a)朝向要处理的构件(10); 具有喷射装置(34)的第三处理单元,用于在待处理的处理构件(10)在空间部分(24)中水平移动之后被降低到含有机脂肪酸的溶液(31)中, 将有机脂肪酸溶液(31)喷洒在要处理的部件(10)上的多余的熔融焊料(5a)上以除去多余的熔融焊料; 以及第四处理单元,用于在有机脂肪酸溶液(31)中水平移动之后向上拉动待处理的处理构件(10),并将待处理的构件从溶液中取出。
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10.METAL PAD STRUCTURE FOR THICKNESS ENHANCEMENT OF POLYMER USED IN ELECTRICAL INTERCONNECTION OF SEMICONDUCTOR DIE TO SEMICONDUCTOR CHIP PACKAGE SUBSTRATE WITH SOLDER BUMP 审中-公开
Title translation: 用于半导体芯片的半导体芯片封装衬底的电气互连中使用的聚合物的金属焊盘结构与焊接BUMP公开(公告)号:WO2013074178A1
公开(公告)日:2013-05-23
申请号:PCT/US2012/052749
申请日:2012-08-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , DAUBENSPECK, Timothy, H. , GAMBINO, Jeffrey, P. , MUZZY, Christopher, D. , QUESTAD, David, L. , SAUTER, Wolfgang , SULLIVAN, Timothy, D.
Inventor: DAUBENSPECK, Timothy, H. , GAMBINO, Jeffrey, P. , MUZZY, Christopher, D. , QUESTAD, David, L. , SAUTER, Wolfgang , SULLIVAN, Timothy, D.
IPC: H01L23/48
CPC classification number: H01L23/3171 , H01L23/3192 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/02126 , H01L2224/02235 , H01L2224/0401 , H01L2224/05019 , H01L2224/05022 , H01L2224/05166 , H01L2224/05171 , H01L2224/05552 , H01L2224/05556 , H01L2224/05558 , H01L2224/05582 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/06051 , H01L2224/061 , H01L2224/0612 , H01L2224/06131 , H01L2224/13007 , H01L2224/13017 , H01L2224/13027 , H01L2224/13111 , H01L2224/1312 , H01L2224/14051 , H01L2224/141 , H01L2224/16225 , H01L2224/81191 , H01L2224/81801 , H01L2924/00 , H01L2924/15311 , H01L2924/351 , H01L2924/3512 , H01L2924/01047 , H01L2924/01029 , H01L2924/01082 , H01L2924/01083 , H01L2924/01049 , H01L2924/00014 , H01L2924/01074 , H01L2924/00012
Abstract: A topographical feature (305) is formed proximate to a conductive bond pad (235) that is used to couple a solder bump (160) to a semiconductor die (140). The topographical feature (305) is separated from the conductive bond pad (235) by a gap (310). In one embodiment, the topographical feature (305) is formed at a location that is slightly beyond the perimeter of the solder bump (160), wherein an edge of the bump (160) is aligned vertically to coincide with the gap (310) separating the conductive bond pad (235) from the topographical feature (305). The topographical feature (305) provides thickness enhancement of a non-conductive layer (240) disposed over the semiconductor die (140) and the conductive bond pad (235) and stress buffering.
Abstract translation: 形成靠近用于将焊料凸块(160)耦合到半导体管芯(140)的导电接合焊盘(235)的形貌特征(305)。 地形特征(305)通过间隙(310)与导电接合垫(235)分离。 在一个实施例中,形貌特征(305)形成在稍微超过焊料凸块(160)的周边的位置处,其中凸起(160)的边缘垂直对准,以与间隔(310)分离重合 来自所述形貌特征(305)的所述导电接合焊盘(235)。 形貌特征(305)提供设置在半导体管芯(140)和导电接合焊盘(235)之上的非导电层(240)的厚度增强和应力缓冲。
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