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    MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY PASSIVATIONS USING AN OXYGEN PLASMA
    2.
    发明申请
    MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY PASSIVATIONS USING AN OXYGEN PLASMA 审中-公开
    用氧气等离子体钝化保持高K栅堆栈的完整性

    公开(公告)号：WO2011025800A2

    公开(公告)日：2011-03-03

    申请号：PCT/US2010/046568

    申请日：2010-08-25

    Applicant: GLOBALFOUNDRIES INC. ,  BEYER, Sven ,  CARTER, Rick ,  HELLMICH, Andreas ,  REIMER, Berthold

    Inventor： BEYER, Sven ,  CARTER, Rick ,  HELLMICH, Andreas ,  REIMER, Berthold

    IPC: H01L21/28

    CPC classification number: H01L21/28247 ,  H01L21/0206 ,  H01L21/02244 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/7848

    Abstract: In semiconductor devices, integrity of a titanium nitride material (152) may be increased by exposing the material to an oxygen plasma (110) after forming a thin silicon nitride -based material. The oxygen plasma (110) may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes (111) based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material (152). In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.

    Abstract translation: 在半导体器件中，在形成基于氮化硅的薄基材料之后，通过将材料暴露于氧等离子体（110）可以增加氮化钛材料（152）的完整性。 氧等离子体（110）可导致任何可能未被氮化硅基材料适当覆盖的微小表面部分的附加钝化。 因此，有效的清洁配方，例如基于SPM的清洁工艺（111），可以在附加钝化之后进行，而不会过度损失氮化钛材料（152）。 以这种方式，基于高效清洁工艺，可以用非常薄的保护性内衬材料形成精密的高k金属栅极叠层，而不会过度地促成早期制造阶段的明显的良率损失。

    FINFET STRUCTURES WITH STRESS-INDUCING SOURCE/DRAIN-FORMING SPACERS AND METHODS FOR FABRICATING SAME
    3.
    发明申请
    FINFET STRUCTURES WITH STRESS-INDUCING SOURCE/DRAIN-FORMING SPACERS AND METHODS FOR FABRICATING SAME 审中-公开
    具有应力诱导源/排水成形间隔件的FINFET结构及其制造方法

    公开(公告)号：WO2010144289A1

    公开(公告)日：2010-12-16

    申请号：PCT/US2010/037109

    申请日：2010-06-02

    Applicant: GLOBALFOUNDRIES INC. ,  LUNING, Scott ,  JOHNSON, Frank Scott ,  HARGROVE, Michael J.

    Inventor： LUNING, Scott ,  JOHNSON, Frank Scott ,  HARGROVE, Michael J.

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/7843 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    Abstract: Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins.

    Abstract translation: 本文提供了制造具有应力诱导源极/漏极形成间隔物的FinFET结构和具有这种间隔物的FinFET结构的方法。 在一个实施例中，制造FinFET结构的方法包括制造覆盖半导体衬底的多个平行散热片。 每个翅片都有侧壁。 制造覆盖每个翅片的一部分的栅极结构。 栅极结构在翅片内具有侧壁并覆盖通道。 应力诱导侧壁间隔件围绕翅片的侧壁和门结构的侧壁形成。 应力诱导侧壁间隔物在通道内引起应力。 使用应力诱导侧壁间隔物和栅极结构作为注入掩模将第一导电率确定离子注入到鳍中，以在翅片内形成源区和漏区。

    PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL
    5.
    发明申请
    PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL 审中-公开
    基于硅/碳材料的PMOS和NMOS晶体管的性能增强

    公开(公告)号：WO2010014246A1

    公开(公告)日：2010-02-04

    申请号：PCT/US2009/004417

    申请日：2009-07-31

    Applicant: GLOBALFOUNDRIES INC. ,  HOENTSCHEL, Jan ,  PAPAGEORGIOU, Vassilios ,  HANNON, Belinda

    Inventor： HOENTSCHEL, Jan ,  PAPAGEORGIOU, Vassilios ,  HANNON, Belinda

    IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/265 ,  H01L29/78

    CPC classification number: H01L27/092 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

    Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type (150P, 150N) on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities (103P, 103N) prior to forming the corresponding strained semiconductor alloy (153), thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor (150P) and an N-channel transistor (150N), while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.

    Abstract translation: 可以在适当的制造方案的基础上，在不同导电类型（150P，150N）的晶体管中提供硅/锗材料和硅/碳材料，而不会不利地导致整个工艺的复杂性。 此外，在形成相应的应变半导体合金（153）之前，可以通过空腔（103P，103N）的暴露的表面区域提供适当的注入物质，从而另外有助于增强整体晶体管性能。 在其他实施例中，可以在P沟道晶体管（150P）和N沟道晶体管（150N）中形成硅/碳材料，而相应的拉伸应变分量可以通过在P中的应力记忆技术过度补偿 通道晶体管。 因此，可以将诸如增强P沟道晶体管的整体掺杂物分布的碳物质的有益效果与有效的应变分量组合，同时可以实现增强的整体工艺均匀性。

    SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STRUCTURE ALLOWING ELECTRICAL MEASUREMENTS DURING THE FABRICATION PROCESS
    6.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STRUCTURE ALLOWING ELECTRICAL MEASUREMENTS DURING THE FABRICATION PROCESS 审中-公开
    在制造过程中包含芯片内部电气测试结构允许电气测量的半导体器件

    公开(公告)号：WO2009145907A1

    公开(公告)日：2009-12-03

    申请号：PCT/US2009/003293

    申请日：2009-05-30

    Applicant: GLOBALFOUNDRIES INC. ,  GRILLBERGER, Michael ,  LEHR, Matthias

    Inventor： GRILLBERGER, Michael ,  LEHR, Matthias

    IPC: H01L23/58 ,  H01L23/544

    CPC classification number: H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A test structure or a circuit element acting temporarily as a test structure may be provided within the die region (210) of sophisticated semiconductor devices, while probe pads (241A, 241B) may be located in the frame (230) in order to not unduly consume valuable die area. The electrical connection between the test structure and the probe pads (241A, 241B) may be established by a conductive path (245, 246) including a buried portion (245A, 246A), which extends from the die region (210) into the frame below a die seal (220), thereby maintaining the electrical and mechanical characteristics of the die seal (220).

    Abstract translation: 作为测试结构临时作用的测试结构或电路元件可以设置在复杂半导体器件的管芯区域（210）内，而探针焊盘（241A，241B）可以位于框架（230）中，以便不适当地 消耗宝贵的死区。 测试结构和探针焊盘（241A，241B）之间的电连接可以通过包括埋入部分（245A，246A）的导电路径（245,246）来建立，该掩埋部分从模具区域（210）延伸到框架 在模具密封件（220）下方，从而保持模具密封件（220）的电气和机械特性。

    PROCESS TO REMOVE NI AND PT RESIDUES FOR NIPTSI APPLICATIONS
    7.
    发明申请
    PROCESS TO REMOVE NI AND PT RESIDUES FOR NIPTSI APPLICATIONS 审中-公开
    删除NI和PT残留的NIPTSI应用程序

    公开(公告)号：WO2013074278A1

    公开(公告)日：2013-05-23

    申请号：PCT/US2012/062488

    申请日：2012-10-29

    Applicant: INTERMOLECULAR, INC. ,  GLOBALFOUNDRIES INC.

    Inventor： DUONG, Anh ,  BARSTOW, Sean ,  FITZ, Clemens ,  FOSTER, John ,  KARLSSON, Olov ,  LI, Bei ,  MAVRINAC, James

    IPC: H01L21/336 ,  H01L21/28

    CPC classification number: H01L21/02068 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

    Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.

    Abstract translation: 本发明公开了一种在镍铂硅化过程中清除半导体衬底的残留物的方法。 本发明的实施方案提供了一种多步骤清洁方法，包括在第一次退火之后将基底暴露于硝酸溶液，然后在第二次退火之后暴露于王水溶液。 可以将底物任选地暴露于盐酸溶液中以完全除去任何剩余的铂残余物。

    WORK FUNCTION ADJUSTMENT IN HIGH-K GATES STACKS INCLUDING GATE DIELECTRICS OF DIFFERENT THICKNESS
    8.
    发明申请
    WORK FUNCTION ADJUSTMENT IN HIGH-K GATES STACKS INCLUDING GATE DIELECTRICS OF DIFFERENT THICKNESS 审中-公开
    包括不同厚度的门电介质的高K栅格堆栈中的工作功能调整

    公开(公告)号：WO2011025804A1

    公开(公告)日：2011-03-03

    申请号：PCT/US2010/046572

    申请日：2010-08-25

    Applicant: GLOBALFOUNDRIES INC. ,  SCHEIPER, Thilo ,  WEI, Andy ,  TRENTZSCH, Martin

    Inventor： SCHEIPER, Thilo ,  WEI, Andy ,  TRENTZSCH, Martin

    IPC: H01L21/8234 ,  H01L21/8238

    CPC classification number: H01L21/823462 ,  H01L21/823857

    Abstract: In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species (254A) within the high-k dielectric material (253) with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species (254A), the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures (250A, 250B) may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors (260A, 260B) having a different thickness gate dielectric material may be avoided.

    Abstract translation: 在复杂的制造技术中，通过在高k电介质材料（253）内提供基本上相同的空间分布的功能调节物质（254A）的功函数，可以在早期制造阶段调整工作功能和晶体管元件的阈值电压 在不同厚度的栅极电介质材料中。 在加入功函数调整物质（254A）之后，可以通过选择性地形成额外的电介质层来调节栅介电材料的最终厚度，使得栅电极结构（250A，250B）的进一步构图可以用 与常规制造技术的高度兼容性。 因此，可以避免用于重新调整具有不同厚度栅极电介质材料的晶体管（260A，260B）的阈值电压的非常复杂的过程。

    METHODS FOR FABRICATING MOS DEVICES HAVING EPITAXIALLY GROWN STRESS-INDUCING SOURCE AND DRAIN REGIONS
    10.
    发明申请
    METHODS FOR FABRICATING MOS DEVICES HAVING EPITAXIALLY GROWN STRESS-INDUCING SOURCE AND DRAIN REGIONS 审中-公开
    用于制造具有外源性应力诱导源和排水区的MOS器件的方法

    公开(公告)号：WO2010085757A1

    公开(公告)日：2010-07-29

    申请号：PCT/US2010/021999

    申请日：2010-01-25

    Applicant: GLOBALFOUNDRIES INC. ,  PAL, Rohit ,  YANG, Frank Bin

    Inventor： PAL, Rohit ,  YANG, Frank Bin

    IPC: H01L21/8234 ,  H01L21/8238

    CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84

    Abstract: Methods of fabricating a semiconductor device (100) on and in a semiconductor substrate (110) having a first region (180) and a second region (200) are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack (124) overlying the first region (180) and a second gate stack (128) overlying the second region (200), etching into the substrate (110) first recesses (142) and second recesses (142), the first recesses (142) aligned at least to the first gate stack (124) in the first region (180), and the second recesses (142) aligned at least to the second gate stack (128) in the second region (200), epitaxially growing a first stress-inducing monocrystalline material (150) in the first and second recesses (142), removing the first stress-inducing monocrystalline material (150) from the first recesses (142), and epitaxially growing a second stress-inducing monocrystalline material (170) in the first recesses (142), wherein the second stress-inducing monocrystalline material (170) has a composition different from the first stress-inducing monocrystalline material (150).

    Abstract translation: 提供了在具有第一区域（180）和第二区域（200）的半导体衬底（110）之上和之中制造半导体器件（100）的方法。 根据本发明的示例性实施例，一种方法包括形成覆盖第一区域（180）的第一栅极堆叠（124）和覆盖第二区域（200）的第二栅极叠层（128），蚀刻到衬底（110） ）第一凹部（142）和第二凹部（142），所述第一凹部（142）至少对准所述第一区域（180）中的所述第一栅极堆叠（124），并且所述第二凹部（142）至少对准 在第二区域（200）中的第二栅极堆叠（128），在第一和第二凹部（142）中外延生长第一应力诱导单晶材料（150），从第一和第二区域移除第一应力诱导单晶材料（150） 凹陷（142），并且在第一凹槽（142）中外延生长第二应力诱导单晶材料（170），其中第二应力诱导单晶材料（170）具有不同于第一应力诱导单晶材料 150）。

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