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公开(公告)号：WO2023088649A1
公开(公告)日：2023-05-25
申请号：PCT/EP2022/079894
申请日：2022-10-26
Applicant: ASML NETHERLANDS B.V.
Inventor： CHENG, Jin , CHEN, Feng , ZHENG, Leiwu , FAN, Yongfa , LU, Yen-Wen , WANG, Jen-Shiang , MA, Ziyang , ZHU, Dianwen , CHEN, Xi , ZHAO, Yu
Abstract: An etch bias direction is determined based on a curvature of a contour in a substrate pattern. The etch bias direction is configured to be used to enhance an accuracy of a semiconductor patterning process relative to prior patterning processes. In some embodiments, a representation of the substrate pattern is received, which includes the contour in the substrate pattern. The curvature of the contour of the substrate pattern is determined, and an etch bias direction is determined based on the curvature by considering the curvatures of adjacent contour portions. A simulation model is used to determine an etch effect based on the etch bias direction for an etching process on the substrate pattern.
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公开(公告)号：WO2018153884A1
公开(公告)日：2018-08-30
申请号：PCT/EP2018/054212
申请日：2018-02-21
Applicant: ASML NETHERLANDS B.V.
Inventor： FAN, Yongfa , ZHENG, Leiwu , FENG, Mu , ZHAO, Qian , WANG, Jen-Shiang
IPC: G03F7/20
Abstract: A method involving determining an etch bias for a pattern to be etched using an etch step of a patterning process based on an etch bias model, the etch bias model including a formula having a variable associated with a spatial property of the pattern or with an etch plasma species concentration of the etch step, and including a mathematical term including a natural exponential function to the power of a parameter that is fitted or based on an etch time of the etch step; and adjusting the patterning process based on the determined etch bias.
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公开(公告)号：WO2020193095A1
公开(公告)日：2020-10-01
申请号：PCT/EP2020/055785
申请日：2020-03-05
Applicant: ASML NETHERLANDS B.V.
Inventor： MA, Ziyang , CHENG, Jin , LUO, Ya , ZHENG, Leiwu , GUO, Xin , WANG, Jen-Shiang , FAN, Yongfa , CHEN, Feng , CHEN, Yi-Yin , ZHANG, Chenji , LU, Yen-Wen
Abstract: A method for training a patterning process model, the patterning process model configured to predict a pattern that will be formed on a patterning process. The method involves obtaining an image data associated with a desired pattern, a measured pattern of the substrate, a first model comprising a first set of parameters, and a machine learning model comprising a second set of parameters; and iteratively determining values of the first set of parameters and the second set of parameters to train the patterning process model. An iteration involves executing, using the image data, the first model and the machine learning model to cooperatively predict a printed pattern of the substrate; and modifying the values of the first set of parameters and the second set of parameters such that a difference between the measured pattern and the predicted pattern of the patterning process model is reduced.
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公开(公告)号：WO2018033363A1
公开(公告)日：2018-02-22
申请号：PCT/EP2017/069068
申请日：2017-07-27
Applicant: ASML NETHERLANDS B.V.
Inventor： FAN, Yongfa , FENG, Mu , ZHENG, Leiwu , ZHAO, Qian , WANG, Jen-Shiang
IPC: G03F7/20
CPC classification number: G03F7/70616 , G03F7/70425 , G03F7/70433 , G03F7/705
Abstract: Provided is a process to model post-exposure effects in patterning processes, the process including: obtaining, with one or more processors, values based on measurements of structures formed on one or more substrates by a post-exposure process and values of a first pair of process parameters by which process conditions were varied; modeling, with one or more processors, as a surface, correlation between the values based on measurements of the structures and the values of the first pair of process parameters; and storing, with one or more processors, the model in memory.
Abstract translation: 提供了一种在构图过程中对后曝光效果进行建模的过程，该过程包括：利用一个或多个处理器获得基于对由一个或多个基板形成的结构的测量值的值， 暴露过程和第一对过程参数的值，通过该过程参数改变过程条件; 使用一个或多个处理器作为表面，建模基于结构的测量值和第一对处理参数的值之间的相关性; 并用一个或多个处理器将模型存储在内存中。
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Patent Agency Ranking
公开(公告)号：WO2023088641A1
公开(公告)日：2023-05-25
申请号：PCT/EP2022/079676
申请日：2022-10-24
Applicant: ASML NETHERLANDS B.V.
Inventor： REN, Jiaxing , CHEN, Yi-Yin , FAN, Yongfa , LIANG, Jiao
Abstract: A grid dependency check for a simulation model is described. According to embodiments of the present disclosure, a grid dependency check can be advantageously performed faster and more efficiently compared to prior grid dependency checks. Certain portions of a design layout are selected and cropped to the minimum size required by the model, and used to generate a second design layout. 5 The selected portions are rotated and/or shifted relative to the grid to form one or more moved portions. The second design layout includes the one or more selected portions and the one or more moved portions so that a modeling operation (e.g., model apply) needs to only run a single time instead of multiple times as in the prior grid dependency checks.
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公开(公告)号：WO2021228725A1
公开(公告)日：2021-11-18
申请号：PCT/EP2021/062227
申请日：2021-05-07
Applicant: ASML NETHERLANDS B.V.
Inventor： HUANG, Jiao , ZHENG, Yunan , ZHAO, Qian , LIANG, Jiao , FAN, Yongfa , FENG, Mu
Abstract: Systems and methods for determining one or more characteristic metrics for a portion of a pattern on a substrate are described. Pattern information for the pattern on the substrate is received. The pattern on the substrate has first and second portions. The first portion (404A,406B) of the pattern is blocked (400,402), for example with a geometrical block mask (408,410), based on the pattern information, such that the second portion of the pattern remains unblocked. The one or more metrics are determined for the unblocked second portion of the pattern. In some embodiments, the first and second portions of the pattern correspond to different exposures in a semiconductor lithography process. The semiconductor lithography process may be a multiple patterning technology process, for example, such as a double patterning process, a triple patterning process, or a spacer double patterning process.
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7.发明申请
公开(公告)号：WO2023084063A1
公开(公告)日：2023-05-19
申请号：PCT/EP2022/081686
申请日：2022-11-12
Applicant: ASML NETHERLANDS B.V.
Inventor： REN, Jiaxing , FAN, Yongfa , CHEN, Yi-Yin , ZHANG, Chenji , ZHENG, Leiwu
IPC: G03F7/20
Abstract: Machine learning models can be trained to predict imaging characteristics with respect to variation in a pattern on a wafer resulting from a patterning process. However, due to low pattern coverage provided by limited wafer data used for training, machine learning models tend to overfit, and predictions from the machine learning models deviate from physical trends that characterize the pattern on the wafer and/or the patterning process with respect to the pattern variation. To enhance pattern coverage, training data is augmented with pattern data that conforms to a certain expected physical trend, and applies to new patterns not covered by previously measured wafer data.
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8.发明申请
公开(公告)号：WO2022268434A1
公开(公告)日：2022-12-29
申请号：PCT/EP2022/064507
申请日：2022-05-29
Applicant: ASML NETHERLANDS B.V.
Inventor： HUANG, Jiao , WANG, Jinze , YAN, Yan , FAN, Yongfa , LIU, Liang , FENG, Mu
IPC: G03F7/20 , G03F7/70441 , G03F7/705 , G03F7/70625
Abstract: Etch bias is determined based on a curvature of a contour in a substrate pattern. The etch bias is configured to be used to enhance an accuracy of a semiconductor patterning process relative to prior patterning processes. In some embodiments, a representation of the substrate pattern is received, which includes the contour in the substrate pattern. The curvature of the contour of the substrate pattern is determined and inputted to a simulation model. The simulation model comprises a correlation between etch biases and curvatures of contours. The etch bias for the contour in the substrate pattern is outputted by the simulation model based on the curvature.
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公开(公告)号：WO2021032448A1
公开(公告)日：2021-02-25
申请号：PCT/EP2020/071742
申请日：2020-08-01
Applicant: ASML NETHERLANDS B.V.
Inventor： ZHENG, Yunan , FAN, Yongfa , FENG, Mu , ZHENG, Leiwu , WANG, Jen-Shiang , LUO, Ya , ZHANG, Chenji , CHEN, Jun , HOU, Zhenyu , WANG, Jinze , CHEN, Feng , MA, Ziyang , GUO, Xin , CHENG, Jin
IPC: G03F7/20
Abstract: Described herein are method generating modified simulated contours and/or generate metrology gauges based on the modified contours. A method of generating metrology gauges for measuring a physical characteristic of a structure on a substrate includes obtaining (i) measured data associated with the physical characteristic of the structure printed on the substrate, and (ii) at least portion of a simulated contour of the structure, the portion of the simulated contour being associated with the measured data; modifying, based on the measured data, the portion of the simulated contour of the structure; and generating the metrology gauges on or adjacent to the modified portion of the simulated contour, the metrology gauges being placed to measure the physical characteristic of the simulated contour of the structure.
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