公开(公告)号：WO2013003348A1

公开(公告)日：2013-01-03

申请号：PCT/US2012/044199

申请日：2012-06-26

Applicant: CREE, INC. ,  NORTH CAROLINA STATE UNIVERSITY ,  DHAR, Sarit ,  CHENG, Lin ,  RYU, Sei-Hyung ,  AGARWAL, Anant, Kumar ,  PALMOUR, John, Williams ,  MAKI, Erik ,  GURGANUS, Jason ,  LICHTENWALNER, Daniel, Jenner

Inventor： DHAR, Sarit ,  CHENG, Lin ,  RYU, Sei-Hyung ,  AGARWAL, Anant, Kumar ,  PALMOUR, John, Williams ,  MAKI, Erik ,  GURGANUS, Jason ,  LICHTENWALNER, Daniel, Jenner

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/314 ,  H01L21/331 ,  H01L21/336 ,  H01L29/16

CPC classification number: H01L29/7802 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/02378 ,  H01L21/045 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7813

Abstract: Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

Abstract translation: 公开了具有增加的信道移动性的半导体器件及其制造方法的实施例。 在一个实施例中，半导体器件包括在沟道区上的衬底上包括沟道区和栅叠层的衬底。 栅极堆叠包括碱土金属。 在一个实施方案中，碱土金属是钡（Ba）。 在另一个实施方案中，碱土金属是锶（Sr）。 碱土金属导致半导体器件的沟道迁移率的显着改善。

公开(公告)号：WO2012118566A1

公开(公告)日：2012-09-07

申请号：PCT/US2012/020494

申请日：2012-01-06

Applicant: CREE, INC.

Inventor： DHAR, Sarit ,  RYU, Sei-Hyung ,  CHENG, Lin ,  AGARWAL, Anant, K.

IPC: H01L29/10

CPC classification number: H01L29/107 ,  H01L21/225 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/66568

Abstract: Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.

Abstract translation: 公开了具有高性能通道的半导体器件及其制造方法。 优选地，半导体器件是金属氧化物半导体（MOS）器件，并且甚至更优选半导体器件是碳化硅（SiC）MOS器件。 在一个实施例中，半导体器件包括第一导电类型的SiC衬底，第二导电类型的第一阱，第二导电类型的第二阱以及形成在第二导电类型的表面处的第二导电类型的表面扩散沟道 半导体器件在第一和第二阱之间。 控制表面扩散通道的深度和掺杂浓度，以便在处于导通状态同时保持导通状态或阈值时，与没有表面扩散沟道区的相同半导体器件相比，为半导体器件提供增加的载流子迁移率， 电压提供常态动作。

公开(公告)号：WO2015050615A2

公开(公告)日：2015-04-09

申请号：PCT/US2014/046505

申请日：2014-07-14

Applicant: CREE, INC.

Inventor： LICHTENWALNER, Daniel, Jenner ,  CHENG, Lin ,  AGARWAL, Anant, Kumar ,  PALMOUR, John, Williams

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42368 ,  H01L21/045 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7813

Abstract: The present disclosure relates to a silicon carbide (SiC) field effect device that has a gate assembly formed in a trench. The gate assembly includes a gate dielectric that is an dielectric layer, which is deposited along the inside surface of the trench and a gate dielectric formed over the gate dielectric. The trench extends into the body of the device from a top surface and has a bottom and side walls that extend from the top surface of the body to the bottom of the trench. The thickness of the dielectric layer on the bottom of the trench is approximately equal to or greater than the thickness of the dielectric layer on the side walls of the trench.

Abstract translation: 本发明涉及一种在沟槽中形成栅极组件的碳化硅（SiC）场效应器件。 栅极组件包括栅极电介质，栅极电介质是沿着沟槽的内表面沉积的电介质层和形成在栅极电介质上的栅极电介质。 沟槽从顶表面延伸到装置的主体中，并且具有从主体的顶表面延伸到沟槽底部的底壁和侧壁。 沟槽底部的电介质层的厚度大致等于或大于沟槽侧壁上的电介质层的厚度。

公开(公告)号：WO2015021154A1

公开(公告)日：2015-02-12

申请号：PCT/US2014/049941

申请日：2014-08-06

Applicant: CREE, INC.

Inventor： PALA, Vipindas ,  AGARWAL, Anant, Kumar ,  CHENG, Lin ,  LICHTENWALNER, Daniel, Jenner ,  PALMOUR, John, Williams

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0684 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7827

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

Abstract translation: 功率金属氧化物半导体场效应晶体管（MOSFET）包括衬底，衬底上的漂移层以及漂移层上的扩散层。 扩展层包括由结栅场效应（JFET）区域分隔的一对结植入物。 栅极氧化层位于扩散层的顶部。 栅极接触位于栅极氧化物层的顶部。 源触点中的每一个位于扩散层的与栅极氧化物层和栅极接触分离的部分上。 漏极接触在衬底的与漂移层相对的表面上。

公开(公告)号：WO2012154288A1

公开(公告)日：2012-11-15

申请号：PCT/US2012/027255

申请日：2012-03-01

Applicant: CREE, INC. ,  RYU, Sei-Hyung ,  CAPELL, Doyle Craig ,  CHENG, Lin ,  DHAR, Sarit ,  JONAS, Charlotte ,  AGARWAL, Anant ,  PALMOUR, John

Inventor： RYU, Sei-Hyung ,  CAPELL, Doyle Craig ,  CHENG, Lin ,  DHAR, Sarit ,  JONAS, Charlotte ,  AGARWAL, Anant ,  PALMOUR, John

IPC: H01L21/336 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7395

Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region.

Abstract translation: 半导体器件包括具有第一导电类型的漂移层，漂移层中具有与第一导电类型相反的第二导电类型的阱区以及阱区中的源极区。源极区具有第一导电类型并且限定 在井区域中的通道区域。 源极区域包括与沟道区域相邻的横向源极区域和远离与沟道区域相对的横向源极区域延伸的多个源极接触区域。 具有第二导电类型的体接触区域在多个源极接触区域中的至少两个之间并且与阱区域接触。

公开(公告)号：WO2015042148A1

公开(公告)日：2015-03-26

申请号：PCT/US2014/056094

申请日：2014-09-17

Applicant: CREE, INC.

Inventor： PALA, Vipindas ,  VAN BRUNT, Edward, Robert ,  CHENG, Lin ,  PALMOUR, John, Williams

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16 ,  H01L29/47

CPC classification number: H01L29/7806 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66712

Abstract: A semiconductor device (48) includes a vertical field-effect-transistor (50) and at least two bypass diodes (52). The transistor includes a substrate (54), a drift layer (56) formed over the substrate, a gate contact (72) and a plurality of source contacts (74) located on a first surface of the drift layer opposite the substrate, a drain contact (76) located on a surface of the substrate opposite the drift layer, and a plurality of junction implants (58, 60, 112, 114), each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the bypass diodes are formed by placing a Schottky metal contact (78) on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants.

Abstract translation: 半导体器件（48）包括垂直场效应晶体管（50）和至少两个旁路二极管（52）。 晶体管包括衬底（54），形成在衬底上的漂移层（56），位于漂移层与衬底相对的第一表面上的栅极接触（72）和多个源极接触（74），漏极 位于与漂移层相对的衬底的表面上的接触件（76）和多个接合植入物（58,60,112,114），所述多个结植入物中的每一个在所述漂移体的表面上彼此横向分离 层与衬底相对并向下延伸到衬底。 每个旁路二极管通过将肖特基金属触点（78）放置在漂移层的第一表面上而形成，使得每个肖特基金属触点在多个结植入物中的两个之间延伸。

公开(公告)号：WO2015042146A1

公开(公告)日：2015-03-26

申请号：PCT/US2014/056091

申请日：2014-09-17

Applicant: CREE, INC.

Inventor： PALA, Vipindas ,  CHENG, Lin ,  AGARWAL, Anant, Kumar ,  PALMOUR, John, Williams ,  VAN BRUNT, Edward, Robert

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/336 ,  H01L29/16 ,  H01L29/06 ,  H01L29/47

CPC classification number: H01L29/7806 ,  H01L21/046 ,  H01L21/26506 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7828 ,  H01L29/8611 ,  H01L29/872

Abstract: A semiconductor device comprising a vertical field-effect transistor (60) and a bypass diode (62) connected between a source contact (86) and a drain contact (88) of the transistor. According to one embodiment, the transistor includes a pair of junction implants (70) separated by a junction field-effect transistor region (72). At least one of the junction implants includes a deep well region (74) that is shared with the bypass diode, such that the shared deep well region functions as both a source junction in the transistor and a junction barrier region in the bypass diode. The transistor and the bypass diode may include a substrate (64), a drift layer (66) over the substrate, and a spreading layer (68) over the drift layer, such that the junction implants are formed in the spreading layer. The bypass diode may be a junction barrier Schottky (JBS) diode.

Abstract translation: 一种半导体器件，包括连接在晶体管的源极触点（86）和漏极触点（88）之间的垂直场效应晶体管（60）和旁路二极管（62）。 根据一个实施例，晶体管包括由结型场效应晶体管区域（72）分开的一对结植入物（70）。 连接植入物中的至少一个包括与旁路二极管共享的深阱区域（74），使得共享的深阱区域用作晶体管中的源极结和旁路二极管中的结阻挡区域。 晶体管和旁路二极管可以包括衬底（64），衬底上的漂移层（66）和漂移层上的扩散层（68），使得在扩散层中形成结植入物。 旁路二极管可以是结垒肖特基（JBS）二极管。

公开(公告)号：WO2015023349A1

公开(公告)日：2015-02-19

申请号：PCT/US2014/041680

申请日：2014-06-10

Applicant: CREE, INC.

Inventor： VAN BRUNT, Edward, Robert ,  PALA, Vipindas ,  CHENG, Lin ,  AGARWAL, Anant, Kumar

IPC: H01L29/861 ,  H01L29/06 ,  H01L21/329 ,  H01L29/24

CPC classification number: H01L29/36 ,  H01L21/0475 ,  H01L21/322 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/732 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7811 ,  H01L29/7823 ,  H01L29/861 ,  H01L29/872

Abstract: Embodiments of a semiconductor die having a semiconductor device implemented on the semiconductor die and an edge termination structure around a periphery of the semiconductor device and methods of fabricating the same. In one embodiment, a semiconductor die includes a semiconductor device and an edge termination structure around a periphery of the semiconductor device, where the edge termination structure includes negative features (trenches and/or divots) that vary dose in a corresponding edge termination region to approximate a desired dose profile. In one embodiment, the desired dose profile is a substantially decreasing or substantially linearly decreasing dose from an edge of a main junction of the semiconductor device to an edge of the edge termination region. In this manner, electric field crowding at the edge of the main junction of the semiconductor device is substantially reduced, which in turn substantially improves a break-down voltage of the semiconductor device.

Abstract translation: 具有在半导体管芯上实现的半导体器件的半导体管芯的实施例和围绕半导体器件的周边的边缘端接结构及其制造方法。 在一个实施例中，半导体管芯包括半导体器件和围绕半导体器件的周边的边缘终端结构，其中边缘终端结构包括在相应边缘终止区域中改变剂量的负特征（沟槽和/或纹理）以近似 期望的剂量分布。 在一个实施例中，期望的剂量分布是从半导体器件的主结的边缘到边缘终止区的边缘的基本上减小或基本线性减小的剂量。 以这种方式，在半导体器件的主结的边缘处拥挤的电场被大大减少，这又大大改善了半导体器件的击穿电压。

公开(公告)号：WO2015013628A2

公开(公告)日：2015-01-29

申请号：PCT/US2014/048217

申请日：2014-07-25

Applicant: CREE, INC.

Inventor： VAN BRUNT, Edward Robert ,  SUVOROV, Alexander V. ,  PALA, Vipindas ,  CHENG, Lin

IPC: H01L29/16 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/047 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7828 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron.

Abstract translation: 根据一些实施例的半导体器件结构包括具有第一导电类型的碳化硅衬底，在碳化硅衬底上具有第一导电类型并且具有与硅相对的上表面的碳化硅漂移层 碳化物衬底，以及碳化硅漂移层中的埋入式结结构。 埋入式结结构具有与第一导电类型相反的第二导电类型，并具有大于约1微米的结深度。

公开(公告)号：WO2015009348A1

公开(公告)日：2015-01-22

申请号：PCT/US2014/038152

申请日：2014-05-15

Applicant: CREE, INC.

Inventor： VAN BRUNT, Edward Robert ,  PALA, Vipindas ,  CHENG, Lin ,  AGARWAL, Anant Kumar

IPC: H01L29/15

CPC classification number: H01L22/12 ,  H01L21/761 ,  H01L22/14 ,  H01L22/20 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/872

Abstract: Methods of forming a power semiconductor device having an edge termination are provided in which the power semiconductor device that has a drift region of a first conductivity type is formed on a substrate. A junction termination extension is formed on the substrate adjacent the power semiconductor device, the junction termination extension including a plurality of junction termination zones that are doped with dopants having a second conductivity type. The junction termination zones have different effective doping concentrations. A dopant activation process is performed to activate at least some of the dopants in the junction termination zones. An electrical characteristic of the power semiconductor device is measured. Then, the junction termination extension is etched in order to reduce the effective doping concentration within the junction termination extension.

Abstract translation: 提供了形成具有边缘终端的功率半导体器件的方法，其中在衬底上形成具有第一导电类型的漂移区的功率半导体器件。 在与功率半导体器件相邻的衬底上形成接合端接延伸部分，接合终端延伸部包括掺杂有具有第二导电类型的掺杂剂的多个接合终端区域。 连接端接区具有不同的有效掺杂浓度。 执行掺杂剂激活过程以激活连接终止区中的至少一些掺杂剂。 测量功率半导体器件的电气特性。 然后，为了降低连接端接延伸部内的有效掺杂浓度，蚀刻了接合端接延伸部。