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    METHOD OF FORMING A CARBON NANOTUBE-BASED CONTACT TO SEMICONDUCTOR
    1.
    发明申请
    METHOD OF FORMING A CARBON NANOTUBE-BASED CONTACT TO SEMICONDUCTOR 审中-公开
    基于碳纳米管的接触到半导体的方法

    公开(公告)号：WO2008115652A1

    公开(公告)日：2008-09-25

    申请号：PCT/US2008/054431

    申请日：2008-02-20

    Applicant: NANTERO, INC. ,  WARD, Jonathan, W. ,  SCHLATKA, Benjamin ,  SMITH, Robert, F. ,  SEGAL, Brent, M.

    Inventor： WARD, Jonathan, W. ,  SCHLATKA, Benjamin ,  SMITH, Robert, F. ,  SEGAL, Brent, M.

    IPC: H01L21/44 ,  B82B1/00

    CPC classification number: H01L33/40 ,  B82Y20/00 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/417 ,  H01L29/452 ,  H01L33/32 ,  Y10S438/924 ,  Y10T428/30 ,  Y10T428/31678

    Abstract: Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided.

    Abstract translation: 制造商在与通常用于光子应用的半导体材料P型氮化镓（p-GaN）形成低电阻欧姆电接触方面遇到限制，使得接触对器件的发光是高度透明的。 碳纳米管（CNT）由于其组合的金属和半导体特性以及CNT的织物具有高的光学透明度的事实，可以解决这个问题。 接触方案的物理结构分为三个部分：a）GaN，b）界面材料和c）金属导体。 界面材料的作用是使GaN和金属两者合适地接触，这样GaN又将与将器件与外部电路接口的金属导体进行良好的电接触。 提供了一种使用CNT和金属制造与GaN接触的方法，同时保持了GaN表面的保护。

    IMPROVED SOLID STATE MICROANEMOMETER
    2.
    发明申请
    IMPROVED SOLID STATE MICROANEMOMETER 审中-公开
    改进的固态微量计

    公开(公告)号：WO1992010726A1

    公开(公告)日：1992-06-25

    申请号：PCT/US1991009335

    申请日：1991-12-12

    Applicant: UNIVERSITY OF CINCINNATI

    Inventor： UNIVERSITY OF CINCINNATI ,  HENDERSON, H., Thurman

    IPC: G01F01/68

    CPC classification number: G01P5/12 ,  G01F1/6845 ,  G01P13/02 ,  G01P2015/084 ,  Y10S438/924

    Abstract: A solid state microanemometer (10) is micromachined from a crystal to a shape with four thick external sides (14, 15, 16, 17) that define an outer rectangle, four thin sections (24, 25, 26, 27) that define an inner rectangle and four diagonally directed branches (18, 19, 20, 21) interconnecting the corners of the outer rectangle to the inner rectangle. Four semiconductor resistors (34, 35, 36, 37) located on the four inner sections (24, 25, 26, 27) form a sensing bridge. Each external side (14, 15, 16, 17) has a pair of electrical contacts (43 and 44, 51 and 52, 59 and 60, 67 and 68) that are electrically interconnected, via conductive leads (39 and 40, 47 and 48, 55 and 56, 63 and 64) that extend along the diagonal branches and partially along the inner sections, to one of the semiconductor resistors (34, 35, 36, 37). The physically connected semiconductor resistors (34, 35, 36, 37) and external sides (14, 15, 16, 17) form a rugged solid state device (10), while thermal and electrical isolation of the resistors (34, 35, 36, 37) from each other permits higher operating temperatures and improved fluid flow sensing capability.

    SILICON ON INSULATOR ACHIEVED USING ELECTROCHEMICAL ETCHING
    4.
    发明申请
    SILICON ON INSULATOR ACHIEVED USING ELECTROCHEMICAL ETCHING 审中-公开
    使用电化学蚀刻实现绝缘子的硅

    公开(公告)号：WO1996039712A1

    公开(公告)日：1996-12-12

    申请号：PCT/US1996007928

    申请日：1996-05-30

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  McCARTHY, Anthony, M.

    Inventor： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    IPC: H01L21/3063

    CPC classification number: H01L21/265 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S438/924 ,  Y10S438/977 ,  Y10S438/98

    Abstract: Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wfers onto support members. The transfer process may be performed at temperatures of 50 DEG C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, radiation-hard circuits and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. Using these techniques, radiation hardened circuits can be produced.

    Abstract translation: 在完成电路制造之后转移块状晶体硅晶片，以在几乎任何支撑件上形成晶体电路薄膜，例如金属，半导体，塑料，聚合物，玻璃，木材和纸。 特别地，该技术适合于形成绝缘体上硅（SOI）晶片，由此，由于硅衬底的移除，所形成的器件和电路在转移之后表现出优异的性能。 传统工艺对传统硅制造的附加成本是微不足道的。 不需要外延，剥离，释放或掩埋氧化物层来执行将单个或多个焊盘转移到支撑构件上。 转印过程可以在50℃或更低的温度下进行，允许电路周围的透明度，并且不需要后转印图案。 因此，该技术为高亮度，高分辨率视频速度彩色显示器，减薄厚度增加灵活性智能卡，超薄支持元件上的柔性电子元件，粘合电子产品，触摸屏幕，开发了集成电路设备的新途径 电子产品，需要低重量材料的物品，智能卡，加密系统智能钥匙，玩具，大面积电路，柔性支架，辐射硬电路等应用。 增加的过程灵活性还允许一种便宜的技术，以增加市场驱动的技术（如微处理器）的电路速度。 使用这些技术，可以生产辐射硬化电路。

    METHOD OF MAKING A MICROMECHANICAL SILICON-ON-GLASS TUNING FORK GYROSCOPE
    9.
    发明申请
    METHOD OF MAKING A MICROMECHANICAL SILICON-ON-GLASS TUNING FORK GYROSCOPE 审中-公开
    制造微波玻璃调理机的方法

    公开(公告)号：WO1995021383A1

    公开(公告)日：1995-08-10

    申请号：PCT/US1995001330

    申请日：1995-02-01

    Applicant: THE CHARLES STARK DRAPER LABORATORY, INC.

    Inventor： THE CHARLES STARK DRAPER LABORATORY, INC. ,  CHO, Steve, T.

    IPC: G01P09/04

    CPC classification number: G01C19/5719 ,  Y10S438/924

    Abstract: A micromechanical tuning fork gyroscope (14) fabricated by a dissolved silicon wafer process whereby electrostatic bonding forms a hermetic seal between an etched glass substrate (12), metal electrodes (202) deposited thereon, and a silicon comb-drive tuning fork gyroscope (14). The dissolved silicon wafer process involves single-sided processing of a silicon substrate (100), including the steps of etching recesses (102), diffusing an etch resistant dopant (104) into the silicon substrate (100), and releasing various components of the silicon gyroscope (14) by etching through the diffusion layer (104) in desired locations (106). The glass substrate (12) also undergoes single-sided processing, including the steps of etching recesses, depositing a multi-metal system in the recesses (200), and selectively etching portions of the multi-metal system (202). One substrate (100) is inverted over the other (12) and aligned before anodic bonding of the two substrates is performed.

    Abstract translation: 通过溶解的硅晶片工艺制造的微机械音叉陀螺仪（14），由此静电接合在蚀刻的玻璃基板（12），沉积在其上的金属电极（202）和硅梳驱动音叉陀螺仪（14）之间形成气密密封 ）。 溶解的硅晶片工艺涉及硅衬底（100）的单面处理，包括蚀刻凹槽（102），将耐蚀刻掺杂剂（104）扩散到硅衬底（100）中的步骤，以及释放 硅陀螺仪（14）通过在所需位置（106）中蚀刻通过扩散层（104）。 玻璃基板（12）也进行单面加工，包括蚀刻凹槽，在凹槽（200）中沉积多金属系统，以及选择性地蚀刻多金属系统（202）的部分的步骤。 一个衬底（100）在另一个衬底（100）上被反转，并且在两个衬底的阳极接合之前进行对准。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
    10.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开
    制造半导体器件的方法

    公开(公告)号：WO1985000695A1

    公开(公告)日：1985-02-14

    申请号：PCT/JP1984000367

    申请日：1984-07-19

    Applicant: SONY CORPORATION ,  KAYANUMA, Akio ,  NAKAMURA, Minoru ,  ASANO, Katsuaki

    Inventor： SONY CORPORATION

    IPC: H01L21/302

    CPC classification number: H01L29/72 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32137 ,  H01L21/32155 ,  Y10S438/924

    Abstract: A method of manufacturing a semiconductor devices makes use of the fact that the isotropic etching rate of a semiconductor layer, e.g., a polycrystalline or amorphous silicon layer, depends upon the doping amount of an impurity in the semiconductor layer. A semiconductor layer (26) formed on a substrate (4) is doped with an impurity such that the impurity concentration distribution is formed in the direction of depth of the semiconductor layer (26). In a region of the semiconductor layer (26) to be selectively removed, anisotropic etching is carried out such that a high-impurity concentration portion is removed and a portion is left in direction of depth of the semiconductor layer (26). Thereafter, the remaining portion is removed by isotropic etching, thereby suppressing side etching.

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