公开(公告)号：WO2006035321A3

公开(公告)日：2006-07-20

申请号：PCT/IB2005003992

申请日：2005-05-05

Applicant: UNITED TEST & ASSEMBLY CT LTD ,  KOLAN RAVI KANTH ,  TAN HIEN BOON ,  SUN YI-SHENG ANTHONY ,  KUAN LIM BENG ,  SHIVALINGAM KRISHNAMURTHY

Inventor： KOLAN RAVI KANTH ,  TAN HIEN BOON ,  SUN YI-SHENG ANTHONY ,  KUAN LIM BENG ,  SHIVALINGAM KRISHNAMURTHY

IPC: H01L23/31

CPC classification number: H01L21/566 ,  H01L23/3114 ,  H01L23/4334 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/013

Abstract: A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free form encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.

Abstract translation: 芯片级集成电​​路封装包括具有第一面和第二面的集成电路芯片。 在集成电路芯片的第一面上形成多个柱状凸块。 封装材料封装集成电路芯片的侧面和第一面以及柱状凸块。 柱状凸块的上端保持游离形式的密封剂材料，并且由密封剂材料的上表面和柱状凸块的上端形成基本平坦的表面。 多个焊球安装在与柱状凸块的上端对应的位置上的基本平坦的表面上。

公开(公告)号：WO2005053373A3

公开(公告)日：2007-12-21

申请号：PCT/IB2004004394

申请日：2004-12-02

Applicant: UNITED TEST AND ASSEMBLY CT ,  TAN HIEN BOON ,  WANG CHUEN KHIANG ,  BIDIN RAHAMAT ,  SUN ANTHONY YI SHENG ,  CHONG DESMOND YOK RUE ,  KOLAN RAVI KANTH

Inventor： TAN HIEN BOON ,  WANG CHUEN KHIANG ,  BIDIN RAHAMAT ,  SUN ANTHONY YI SHENG ,  CHONG DESMOND YOK RUE ,  KOLAN RAVI KANTH

IPC: H01L21/00 ,  H01L29/34 ,  H01L29/40

CPC classification number: H01L23/3114 ,  H01L21/76897 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/8191 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.

Abstract translation: 公开了一种制造芯片级封装的方法。 该方法包括将晶片切割成多个芯片阵列，每个阵列包括两个或多个集成电路芯片。 该方法还包括将每个阵列安装在基板上并将附接到基板的每个阵列切割成单独的芯片级封装，每个单独的芯片级封装仅包括一个集成电路芯片。

公开(公告)号：WO2006035321A2

公开(公告)日：2006-04-06

申请号：PCT/IB2005/003992

申请日：2005-05-05

Applicant: UNITED TEST AND ASSEMBLY CENTER, LTD. ,  KOLAN, Ravi, Kanth ,  TAN, Hien, Boon ,  SUN, Yi-sheng, Anthony ,  KUAN, Lim, Beng ,  SHIVALINGAM, Krishnamurthy

Inventor： KOLAN, Ravi, Kanth ,  TAN, Hien, Boon ,  SUN, Yi-sheng, Anthony ,  KUAN, Lim, Beng ,  SHIVALINGAM, Krishnamurthy

CPC classification number: H01L21/566 ,  H01L23/3114 ,  H01L23/4334 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2224/13099 ,  H01L2924/013 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free form encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.

Abstract translation: 芯片级集成电​​路封装包括具有第一面和第二面的集成电路芯片。 在集成电路芯片的第一面上形成多个柱状凸块。 封装材料封装集成电路芯片的侧面和第一面以及柱状凸块。 柱状凸块的上端保持自由形式的密封剂材料，并且通过密封剂材料的上表面和柱状凸块的上端形成大致平坦的表面。 多个焊球安装在基本平坦的表面上对应于柱形凸块上端的位置上。

公开(公告)号：WO2006028421A1

公开(公告)日：2006-03-16

申请号：PCT/SG2005/000310

申请日：2005-09-09

Applicant: UNITED TEST AND ASSEMBLY CENTER (S) PTE LTD ,  WANG, Chuen Khiang ,  LIU, Hao ,  TAN, Hien Boon ,  LAW, Teik Lyk, Clifton ,  BIDIN, Rahamat ,  SUN, Yi Sheng, Anthony

Inventor： WANG, Chuen Khiang ,  LIU, Hao ,  TAN, Hien Boon ,  LAW, Teik Lyk, Clifton ,  BIDIN, Rahamat ,  SUN, Yi Sheng, Anthony

IPC: H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method for manufacturing integrated circuit packages (100, 200, 300) and a muli-chip integrated circuit package (100, 200, 300) are disclosed. A first die (110) is attached onto a first side of a set of leads of a leadframe (130), an adhesive (350) is applied onto the set of leads at a second side opposite to the first side. A second die (120) is attached onto the adhesive (350). The adhesive fills into the gaps between the leads. The adhesive is then cured. The adhesive attaching the second die fills the a s between the leads so that to avoid formation of internal cavities in the package

Abstract translation: 公开了一种用于制造集成电路封装（100,200,300）和多晶硅集成电路封装（100,200,300）的方法。 第一模具（110）附接到引线框架（130）的一组引线的第一侧上，在与第一侧相对的第二侧处将粘合剂（350）施加到引线组上。 第二模具（120）附接到粘合剂（350）上。 粘合剂填充到引线之间的间隙中。 然后将粘合剂固化。 附着第二模具的粘合剂在引线之间填充a，以避免在封装中形成内部空腔

公开(公告)号：WO2005086234A1

公开(公告)日：2005-09-15

申请号：PCT/SG2005/000067

申请日：2005-03-03

Applicant: UNITED TEST AND ASSEMBLY CENTER LIMITED ,  WANG, Chuen Khiang ,  TAN, Hien Boon ,  TEO, Koon Hwee, Joanne ,  SONG, Sin Nee ,  LUA, Koon Tian, Edmund

Inventor： WANG, Chuen Khiang ,  TAN, Hien Boon ,  TEO, Koon Hwee, Joanne ,  SONG, Sin Nee ,  LUA, Koon Tian, Edmund

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01068 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package including a first substrate having a die receiving area, a first adhesive layer, a window opening, and a plurality of conductive traces, a first semiconductor die having two sides and with an electrically active side mounted to the substrate through the first adheisve layer, a second adhesive layer having a first side attached to an electrically inactive side of the first semiconductor die, a second substrate having a die receiving area and a plurality of conductive traces and terminals, a last adhesive layer having a first side attached to a side of the second substrate with the terminals, a last semiconductor die having two sides and with an electrically inactive side being mounted to the second side of the third adhesive layer, and an electrically active side being electrically coupled to the conductive traces of the first or second substrate directly or through a redistribution device, and an encapsulant to encapsulate the semiconductor dies and electrical coupling, and signal transferring interconnects to transfer an electrical signal from the conductive traces to the exterior of the package.

Abstract translation: 一种半导体封装，包括具有管芯接收区域的第一衬底，第一粘合剂层，窗口和多个导电迹线，具有两侧并且具有电活性侧的第一半导体管芯，其通过第一附着物安装到衬底 层，具有附接到第一半导体管芯的非电活动侧的第一侧的第二粘合剂层，具有管芯接收区域和多个导电迹线和端子的第二基板，最后粘合剂层，其具有附接到第一侧面的第一侧 具有端子的第二衬底的侧面，具有两侧并且具有电惰性侧的最后半导体管芯被安装到第三粘合剂层的第二侧，并且电活性侧电耦合到第一或第二衬底的导电迹线， 第二衬底直接或通过再分布器件，以及密封剂以封装半导体管芯和电c 耦合和信号传输互连以将电信号从导电迹线传送到封装的外部。

公开(公告)号：WO2005053373A2

公开(公告)日：2005-06-16

申请号：PCT/IB2004/004394

申请日：2004-12-02

Applicant: UNITED TEST AND ASSEMBLY CENTER ,  TAN, Hien Boon ,  WANG, Chuen Khiang ,  BIDIN, Rahamat ,  SUN, Anthony Yi Sheng ,  CHONG, Desmond Yok Rue ,  KOLAN, Ravi Kanth

Inventor： TAN, Hien Boon ,  WANG, Chuen Khiang ,  BIDIN, Rahamat ,  SUN, Anthony Yi Sheng ,  CHONG, Desmond Yok Rue ,  KOLAN, Ravi Kanth

CPC classification number: H01L23/3114 ,  H01L21/76897 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/8191 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.

Abstract translation: 公开了一种制造芯片级封装的方法。 该方法包括将晶片切割成多个芯片阵列，每个阵列包括两个或多个集成电路芯片。 该方法还包括将每个阵列安装在基板上并将附接到基板的每个阵列切割成单独的芯片级封装，每个单独的芯片级封装仅包括一个集成电路芯片。