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    INTEGRATED CIRCUIT BUS GRID HAVING WIRES WITH PRE-SELECTED VARIABLE WIDTHS
    96.
    发明公开
    INTEGRATED CIRCUIT BUS GRID HAVING WIRES WITH PRE-SELECTED VARIABLE WIDTHS 审中-公开
    BUSGITTER用于集成电路与选择性可变宽度LINES

    公开(公告)号：EP1442481A4

    公开(公告)日：2005-03-16

    申请号：EP02776247

    申请日：2002-10-17

    申请人： IBM

    发明人： BUFFET PATRICK H ,  SUN YU H

    IPC分类号： G06F17/50 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L29/73 ,  H01L23/48 ,  H01L23/58 ,  H01L29/40

    CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  Y10S257/923 ,  H01L2924/00

    摘要： An electrical bus grid (108) for an application specific integrated circuit (ASIC) chip (102). The bus grid is generally formed by mutually orthogonal wires (28',30') contained within two metal layer (M6',M7'). The bus grid is located within each of a plurality of contiguous rectangular regions (32'), which are defined by electrical contacts (12'). Due to the regular pattern of the electrical contacts, the bus grids within the contiguous rectangular rgions are identical to one another, such that the bus grid forms a repeatable pattern. The widths of the wires in each of the two metal layers vary depending upon the magnitude of the current carried by the corresponding wire. The magnitude of the current in the power bus may be determined by simulation and modeling performed prior to placement of cells (e.g., 18, 20, 22) within the ASICchip.

    Semiconductor integrated circuit
    97.
    发明公开
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：EP1508917A2

    公开(公告)日：2005-02-23

    申请号：EP04254579.8

    申请日：2004-07-30

    申请人： SHARP KABUSHIKI KAISHA

    发明人： Henmi, Takuya

    IPC分类号： H01L23/58

    CPC分类号： H01L23/57 ,  H01L23/5225 ,  H01L23/552 ,  H01L2224/16145 ,  H01L2924/13091

    摘要： In a semiconductor integrated circuit (100) having a shielding film (1) formed by a material different from at least either of a semiconductor substrate (4) and an interlayer insulating film (7) in thermal expansion coefficient, the shielding film (1) has shielding portions (9) and openings (12), and at least either of a plurality of independent openings (12a) whose circumferences are surrounded by the shielding portions (9) and a plurality of independent shielding portions (11) whose circumferences are surrounded by the openings (12) is present and scattered on the entire surface of a chip. Or, a plurality of openings (12) are present on an optional straight line parallel with the surface (4a) of the semiconductor substrate (4) passing through a portion for shielding circuit devices (21) and circuit wirings (16) in the shielding portions (9).

    摘要翻译： 在具有由热膨胀系数不同于半导体衬底（4）和层间绝缘膜（7）中至少一个的材料形成的屏蔽膜（1）的半导体集成电路（100）中，屏蔽膜（1） 具有屏蔽部分（9）和开口（12），并且其周围被屏蔽部分（9）包围的多个独立开口（12a）中的至少一个和周围被包围的多个独立屏蔽部分（11） 通过开口（12）存在并散布在芯片的整个表面上。 或者，在与半导体衬底（4）的表面（4a）平行的可选直线上存在多个开口（12），该半导体衬底（4）的表面穿过屏蔽电路器件（21）和电路布线（16）的部分 部分（9）。

    A modifiable circuit, methods of use and making thereof
    98.
    发明公开
    A modifiable circuit, methods of use and making thereof 有权
    可修改的电路，使用方法和制造方法

    公开(公告)号：EP1494283A1

    公开(公告)日：2005-01-05

    申请号：EP04013796.0

    申请日：2004-06-11

    申请人： Broadcom Corporation

    发明人： Catalasan, Manolito ,  Rakshani, Vafa J. ,  Spittles, Edmund H. ,  Sippel, Tim ,  Unda, Richard

    IPC分类号： H01L23/544 ,  H01L23/525 ,  H01L23/528 ,  H01L23/58 ,  G06F11/00 ,  G11C17/10

    CPC分类号： G11C17/10 ,  H01L23/544 ,  H01L27/118 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A modifiable circuit for modifying a revision identifier (ID) or default register value, and for coupling at least two adjacent logic blocks in an integrated circuit chip, and methods for manufacturing the same. The circuit comprises a memory cell, a register and a control circuit. The memory cell, which may be termed a "Meta-Memory Cell" (MMCEL), has a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks. The memory cell also has a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is located at the boundary of the at least two adjacent logic blocks. The interconnect is formed between the at least two adjacent logic blocks by at least one of the first and second metal interconnect structures, wherein a state of the interconnect is programmable by altering any one of the plurality of metal layers or any one of a plurality of via layers. The register has a data input, a data output and control inputs. The control circuit is coupled to the control inputs of the register. The control circuit receives a chip reset signal and the memory cell output to thereby force the data output of the register to a default register value that equals the output of the memory cell, regardless of the data input of the register.

    摘要翻译： 一种用于修改修订标识符（ID）或默认寄存器值并用于耦合集成电路芯片中的至少两个相邻逻辑块的可修改电路及其制造方法。 该电路包括存储单元，寄存器和控制电路。 可以被称为“元存储器单元”（MMCEL）的存储器单元具有使用第一多个通孔横穿多个金属层的第一金属互连结构，其中第一金属互连结构位于边界 至少两个相邻逻辑块中的一个。 存储器单元还具有使用第二多个通孔横穿多个金属层的第二金属互连结构，其中第二金属互连结构位于至少两个相邻逻辑块的边界处。 互连通过第一金属互连结构和第二金属互连结构中的至少一个在至少两个相邻的逻辑块之间形成，其中互连的状态可通过改变多个金属层中的任何一个或多个金属层中的任何一个 通过图层。 该寄存器具有数据输入，数据输出和控制输入。 控制电路连接到寄存器的控制输入端。 无论寄存器的数据输入如何，控制电路都接收芯片复位信号和存储器单元输出，从而将寄存器的数据输出强制为与存储器单元的输出相等的默认寄存器值。