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189 条记录 (耗时 0.022 秒)

    VERFAHREN ZUR HERSTELLUNG EINER MIKROELEKTROMECHANISCHEN VORRICHTUNG UND MIKROELEKTROMECHANISCHE VORRICHTUNG
    111.
    发明公开
    VERFAHREN ZUR HERSTELLUNG EINER MIKROELEKTROMECHANISCHEN VORRICHTUNG UND MIKROELEKTROMECHANISCHE VORRICHTUNG 审中-公开
    一种用于生产微机电装置和微机电器件

    公开(公告)号：EP2550234A2

    公开(公告)日：2013-01-30

    申请号：EP11713722.4

    申请日：2011-03-21

    申请人： ELMOS Semiconductor AG

    发明人： TEN-HAVE, Arnd

    IPC分类号： B81C1/00

    CPC分类号： G01L1/16 ,  B81B2201/0264 ,  B81B2207/015 ,  B81C1/00246 ,  B81C1/00626 ,  B81C2203/0735 ,  G01L9/0047 ,  G01L9/0054 ,  G01L9/0098 ,  H01L27/20 ,  H01L29/66075

    摘要： The invention relates to a method for producing a microelectromechanical device in a material substrate suitable for producing integrated electronic components, in particular a semiconductor substrate, wherein a material substrate (12, 14, 16) is provided on which at least one surface structure (26) is to be formed during production of the device. An electronic component (30) is formed in the material substrate (12, 14, 16) using process steps of a conventional method for producing integrated electronic components. A device component (44) defining the position of the electronic component (30) and/or required for the function of the electronic component (30) is selectively formed on the material substrate (12, 14, 16) from an etching stop material acting as an etching stop in case of etching of the material substrate (12, 14, 16) and/or in case of etching of a material layer (52) disposed on the material substrate (12, 14, 16). When the device component (44) of the electronic component (30) is implemented, a boundary region (48) is also formed on the material substrate (12, 14, 16) along at least a partial section of an edge of the surface structure (26), wherein said boundary region bounds said partial section. The material substrate (12, 14, 16) thus implemented is selectively etched for forming the surface structure (26), in that the edge of the bounding region (48) defines the position of the surface structure (26) to be implemented on the material substrate (12, 14, 16).

    IC with pressure sensor and manufacturing method thereof
    112.
    发明公开
    IC with pressure sensor and manufacturing method thereof 审中-公开
    Integrierte Schaltung mit Drucksensor und Herstellungsverfahrendafür

    公开(公告)号：EP2492240A1

    公开(公告)日：2012-08-29

    申请号：EP11155694.0

    申请日：2011-02-23

    申请人： NXP B.V.

    发明人： Merz, Matthias ,  Ponomarev, Youri Victorovitch

    IPC分类号： B81C1/00

    CPC分类号： B81C1/00246 ,  B81B2201/0264 ,  B81B2207/015 ,  B81C2203/0714

    摘要： Disclosed is an integrated circuit (IC) comprising a body (10) including a plurality of circuit elements; and a metallization stack over said circuit elements for interconnecting said circuit elements, wherein the metallization stack comprises a conductive layer portion (22) opposite a flexible further conductive layer portion (24) and separated therefrom by a fluid medium (26), a surface of the said flexible further conductive layer portion being exposed to an external pressure; wherein at least some of the circuit elements are arranged to determining the external pressure by measuring a capacitance across the conductive layer portion and the flexible further conductive layer portion. A method of manufacturing such an IC is also disclosed.

    摘要翻译： 公开了一种集成电路（IC），包括：主体（10），包括多个电路元件; 以及用于互连所述电路元件的所述电路元件上的金属化堆叠，其中所述金属化堆叠包括与柔性的另外的导电层部分（24）相对的导电层部分（22），并通过流体介质（26）与其分离， 所述柔性进一步的导电层部分暴露于外部压力; 其中至少一些电路元件被布置成通过测量导电层部分和柔性的另外的导电层部分的电容来确定外部压力。 还公开了制造这种IC的方法。

    MEMS device with electrosatic discharge protection
    116.
    发明公开
    MEMS device with electrosatic discharge protection 审中-公开
    MEMS-Vorrichtung mit Schutz vor elektrostatischer Entladung

    公开(公告)号：EP2316788A1

    公开(公告)日：2011-05-04

    申请号：EP09174516.6

    申请日：2009-10-29

    申请人： NXP B.V.

    发明人： Koning, Jan Jacob ,  El-Ghorba, Mehdi ,  Van Zwol, Johannes

    IPC分类号： B81C1/00

    CPC分类号： B81C1/00246

    摘要： A method of making a bipolar transistor and/or an ESD device integrated onto the same substrate as the MEMS element uses a single additional mask and dopant step, to form the shallow well of second conductivity type. In particular, after forming a MEMS element (18) using a series of steps including forming a well of a first conductivity type and a step (24) of forming a shallow contact of the same first conductivity type at locations determined by a first mask, a bipolar transistor (16,42) and/or ESD protection device (16) is formed using a step of forming a shallow contact (8,10,40) ofopposite conductivity type at locations determined by a second mask.

    摘要翻译： 制造双相晶体管和/或集成在与MEMS元件相同的衬底上的ESD器件的方法使用单个附加掩模和掺杂剂步骤，以形成第二导电类型的浅阱。 特别地，在使用包括形成第一导电类型的阱的一系列步骤形成MEMS元件（18）和在由第一掩模确定的位置处形成相同的第一导电类型的浅接触的步骤（24）之后， 使用在由第二掩模确定的位置处形成具有相反导电类型的浅接触（8,10,40）的步骤来形成双极晶体管（16,42）和/或ESD保护装置（16）。

    Method for forming MEMS devices having low contact resistance and devices obtained thereof
    117.
    发明公开
    Method for forming MEMS devices having low contact resistance and devices obtained thereof 审中-公开
    一种用于与低接触电阻的MEMS器件和由此获得的器件的形成过程

    公开(公告)号：EP2277823A2

    公开(公告)日：2011-01-26

    申请号：EP10075263.3

    申请日：2010-06-18

    申请人： IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

    发明人： Jain, Ajay ,  Severi, Simone ,  Claes, Gert ,  Heck, John

    IPC分类号： B81C1/00

    CPC分类号： B81C1/00246 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81C2203/0714 ,  B81C2203/0735

    摘要： The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.

    摘要翻译： 本公开提出了用于制造MEMS器件的硅 - 锗层，并通过该硅 - 锗层接触的层之间的低电阻接触的方法，检查作为CMOS金属层或另一种硅 - 锗层，通过对开口 在介电层叠层分离两个层。 的层间形成在该开口中，从而覆盖在该开口的底部的另一个层的暴露表面上的开口的至少侧壁上。 这个中间层可以与所述硅 - 锗层接触包括TiN层。 这个中间层可以在TiN层和层之间进一步包括Ti层被接触。 在另一个实施例该中间层包括与所述硅 - 锗层接触的氮化钽层。 该中间层然后可以进一步包括在TaN层和所述层之间的Ta层被接触。