公开(公告)号：EP3195359A1

公开(公告)日：2017-07-26

申请号：EP15760072.7

申请日：2015-09-01

申请人： SanDisk Technologies LLC

发明人： ZHANG, Yanli ,  ALSMEIER, Johann

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/06 ,  H01L21/02365 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/31 ,  H01L21/32133 ,  H01L21/768 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/0657 ,  H01L29/41775 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in at least one active region, a plurality of semiconductor channels having at least one end portion of each of the plurality of semiconductor channels extending substantially perpendicular to the major surface of the substrate, at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels, and at least one first slit trench extending substantially perpendicular to the major surface of the substrate. Each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region.

摘要翻译： 单片三维NAND串包括在至少一个有源区中基本上平行于衬底的主表面延伸的多个控制栅电极，多个半导体沟道具有延伸到多个半导体沟道中的每一个的至少一个端部 基本上垂直于衬底的主表面;至少一个存储膜，位于多个控制栅电极中的每一个与多个半导体沟道中的每个相应半导体沟道之间;以及至少一个第一狭缝沟槽，基本上垂直于主 基材的表面。 多个控制栅电极中的每一个具有与至少一个有源区中的至少一个第一狭缝沟槽相邻的非线性侧壁。

公开(公告)号：EP2639818A3

公开(公告)日：2017-01-18

申请号：EP13157686.0

申请日：2013-03-04

申请人： Renesas Electronics Corporation

发明人： Kaneoka, Tatsunori ,  Kawahara, Takaaki

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC分类号： H01L27/1157 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device with a nonvolatile memory is provided which has improved electric performance. A memory gate electrode (MG) is formed over a semiconductor substrate (1) via an insulating film (5). The insulating film is an insulating film having a charge storage portion therein, and includes a first silicon oxide film (5a), a silicon nitride film (5b) over the first silicon oxide film, and a second silicon oxide film (5c) over the silicon nitride film. Metal elements (6) exist between the silicon nitride film and the second silicon oxide film, or in the silicon nitride film at a surface density of 1 × 10 13 to 2 × 10 14 atoms/cm 2 .

摘要翻译： 提供具有非易失性存储器的半导体器件，其具有改善的电性能。 存储栅电极（MG）经由绝缘膜（5）形成在半导体衬底（1）上。 绝缘膜是其中具有电荷存储部分的绝缘膜，并且在第一氧化硅膜上方包括第一氧化硅膜（5a），氮化硅膜（5b）和第二氧化硅膜（5c） 氮化硅膜。 在氮化硅膜和第二氧化硅膜之间存在金属元素（6），或者在氮化硅膜中以1×10 13至2×10 14原子/ cm 2的表面密度存在金属元素（6）。

公开(公告)号：EP2947685A1

公开(公告)日：2015-11-25

申请号：EP14861114.8

申请日：2014-04-03

申请人： Silicone Valley Co., Ltd

发明人： YOUN, Kyoungseob

IPC分类号： H01L21/66

CPC分类号： H01L22/32 ,  G01R1/0408 ,  G01R1/0466 ,  G01R3/00 ,  H01L21/02118 ,  H01L21/288 ,  H01L21/321 ,  H01L21/32133

摘要： The present invention relates to a semiconductor test pad used in a semiconductor test, and more specifically, to a semiconductor test pad with stacked metal sheets, which is manufactured by preparing a first sheet using a thin metal plate, etching and stacking and then vertically cutting the first sheet, and a method for manufacturing the same. The semiconductor test pad includes first layers, each of which includes an insulator rectangular in cross section and having a predetermined length along a Y-axis direction, and second layers, each of which includes a plurality of rectangular conductors passing, in a Z-axis direction and at predetermined intervals, through insulators each rectangular in cross section and having the same height along the Z-axis direction as the first layer and the same length along the Y-axis direction, wherein the first layers and the second layers are alternately stacked along the X-axis direction, thus allowing the semiconductor test pad to overall look like a rectangular pad, and wherein first layers are positioned at both end portions along the X-axis.

摘要翻译： 本发明涉及半导体测试中使用的半导体测试垫，更具体地说，涉及一种具有堆叠金属片的半导体测试垫，其通过使用薄金属板制备第一片，蚀刻和堆叠，然后垂直切割 第一片及其制造方法。 半导体测试焊盘包括第一层，每个第一层包括横截面为矩形且具有沿Y轴方向的预定长度的绝缘体，以及第二层，每个第二层包括多个矩形导体，其在Z轴上 方向并且以预定间隔通过绝缘体，每个矩形截面并且沿着Z轴方向具有与第一层相同的高度和沿Y轴方向具有相同的长度，其中第一层和第二层交替堆叠 沿X轴方向，从而允许半导体测试焊盘整体看起来像矩形焊盘，并且其中第一层沿着X轴位于两个端部。

公开(公告)号：EP2933679A1

公开(公告)日：2015-10-21

申请号：EP15164032.3

申请日：2015-04-17

申请人： LG Display Co., Ltd.

发明人： Choi, SunHyun ,  Shin, KiTaeg ,  Jo, ChelHee ,  Roh, TaeYun

IPC分类号： G02F1/1345 ,  G02F1/1333

CPC分类号： H01L21/84 ,  G02F1/133345 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/13458 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/32133 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78669 ,  H01L2021/775 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides an array substrate (10) for a display device and a manufacturing method thereof. A transparent electrode pattern (570) is formed between a source/drain metal pattern (540) and a passivation layer (580) located above the source/drain metal pattern (540), which are formed in a passivation hole area (17) of a nonactive area (12) of the array substrate (10). Accordingly, it is possible to prevent display failure caused by a delamination phenomenon or peel-off of the material of the passivation layer (580) due to the lack of adhesion strength between the metal layer (540) and the passivation layer (580) in the passivation holes (600) in the passivation hole area (17).

摘要翻译： 本公开内容提供了一种用于显示装置的阵列基板（10）及其制造方法。 在源极/漏极金属图案（540）和位于源极/漏极金属图案（540）上方的钝化层（580）之间形成透明电极图案（570），其形成在钝化孔区域（17）中 阵列基板（10）的非活性区域（12）。 因此，可以防止由于金属层（540）和钝化层（580）之间的粘合强度不足而导致的钝化层（580）的材料的分层现象或剥离引起的显示故障 钝化孔区域（17）中的钝化孔（600）。

公开(公告)号：EP2815431A4

公开(公告)日：2015-10-14

申请号：EP12875962

申请日：2012-04-30

申请人： HEWLETT PACKARD DEVELOPMENT CO

发明人： GE NING ,  GHOZEIL ADAM L ,  HO CHAW SING ,  BENJAMIN TRUDY

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L27/11517 ,  G11C16/0425 ,  H01L21/28158 ,  H01L21/288 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1156 ,  H01L29/1033 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7884

摘要： A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area.

公开(公告)号：EP2883239A2

公开(公告)日：2015-06-17

申请号：EP13802420.3

申请日：2013-09-24

申请人： Toyota Jidosha Kabushiki Kaisha

发明人： FUJIWARA, Hirokazu ,  SOEJIMA, Narumasa

IPC分类号： H01L21/04

CPC分类号： H01L21/0485 ,  H01L21/30604 ,  H01L21/32133

摘要： A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate (4); widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming, an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.

摘要翻译： 一种半导体器件的制造方法，包括：通过在SiC半导体衬底（4）的表面上的绝缘层的开口的内侧上沉积作为电极材料的金属来形成电金属层; 通过在形成电极金属层之后刻蚀绝缘层来扩大形成在绝缘层中的开口中的内壁表面和电极金属层之间的间隙; 以及在绝缘层被蚀刻之后，通过加热SiC半导体基板和金属电极层，在电极金属层和SiC半导体基板之间形成欧姆接触。

公开(公告)号：EP2715787A2

公开(公告)日：2014-04-09

申请号：EP12792601.2

申请日：2012-05-23

申请人： Micron Technology, Inc.

发明人： FREEMAN, Eric H. ,  SMITH, Michael A.

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L23/528 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76892 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

摘要翻译： 公开了用于形成半导体结构的方法，包括形成导电材料组和绝缘材料的方法，在组上形成第一掩模，形成第一数量的接触区域，在组的第一区域上形成第二掩模， 以及在与所述第一区域横向相邻的第二暴露区域中从所述组中移除材料以形成第二数量的接触区域。 另一种方法包括在导电材料和绝缘材料组的部分上形成第一和第二接触区域，每个第二接触区域比每个第一接触区域更靠近下面的衬底。 还公开了诸如包括横向相邻的第一和第二区域的存储器件的装置，每个区域包括多个导电材料的不同部分的接触区域和形成这种器件的相关方法。

公开(公告)号：EP3238235A4

公开(公告)日：2018-07-25

申请号：EP14909243

申请日：2014-12-23

申请人： INTEL CORP

发明人： SHUSTERMAN YURIY V ,  GRIGGIO FLAVIO ,  INDUKURI TEJASWI K ,  BRAIN RUTH A

IPC分类号： H01L21/3205 ,  H01L21/203 ,  H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/76847 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：EP3286784A1

公开(公告)日：2018-02-28

申请号：EP16730988

申请日：2016-06-10

申请人： SANDISK TECHNOLOGIES LLC

发明人： LU ZHENYU ,  MAO DAXIN ,  ZHANG TONG ,  ALSMEIER JOHANN ,  SHI WENGUANG ,  CHIEN HENRY

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of forming a three-dimensional memory device, includes forming a lower stack structure of insulating and first sacrificial material layers over a substrate, forming first memory openings through the lower stack structure and filling the first memory openings with a sacrificial fill material, replacing the first sacrificial material layers with first electrically conductive layers, forming an upper stack structure of insulating and second sacrificial material layers over the lower stack structure after replacing the first sacrificial material layers, forming second memory openings through the upper stack structure in areas overlying the first memory openings, replacing the second sacrificial material layers with second electrically conductive layers, removing the sacrificial fill material from the first memory openings underneath the second memory openings to form inter-stack memory openings after replacing the second sacrificial material layers, and forming memory stack structures within the inter-stack memory openings.

公开(公告)号：EP3183753A4

公开(公告)日：2018-01-10

申请号：EP15833032

申请日：2015-08-19

申请人： VISHAY-SILICONIX

发明人： SHIBIB M AYMAN ,  ZHANG WENJIE

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/40

CPC分类号： G01R19/15 ,  G01R19/0092 ,  H01L21/02129 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/823487 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7827

摘要： Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.