公开(公告)号：EP0642137B1

公开(公告)日：2001-11-28

申请号：EP94202481.1

申请日：1994-08-31

Applicant: Koninklijke Philips Electronics N.V.

Inventor： Sachdev, Mamoj, c/o Int, Octrooibureau B.V.

IPC: G11C29/00

CPC classification number: G11C29/50016 ,  G11C11/401 ,  G11C11/41 ,  G11C29/34 ,  G11C29/50 ,  G11C2029/5006

Abstract: An electronic circuit includes an array of a plurality of memory cells that are functionally organized in rows and columns. The circuit comprises test means that are selectively operative to access all cells of the array in parallel. An IDDQ-test then discovers whether or not there is a defect in any of the cells.

公开(公告)号：EP0686979B1

公开(公告)日：2001-03-07

申请号：EP94830283.1

申请日：1994-06-10

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Camerlenghi, Emilio

IPC: G11C29/00 ,  G11C16/06 ,  G06F11/20

CPC classification number: G11C29/82 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/34 ,  G11C29/50 ,  G11C2029/5006

公开(公告)号：EP0698273B1

公开(公告)日：2000-05-10

申请号：EP95907132.5

申请日：1995-02-15

Applicant: Koninklijke Philips Electronics N.V.

Inventor： SACHDEV, Manoj

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C8/04 ,  G11C8/12 ,  G11C11/41 ,  G11C29/34 ,  G11C2029/5006

Abstract: An SRAM has a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The SRAM comprises IDDQ test means to render the word lines active in parallel by cumulatively increasing a number of active ones among the word lines. This permits the writing of a specific logic state in all cells of a column through the tiny bit line drivers that are progressively assisted by the cells already written, thus avoiding the use of additional heavy write circuitry for IDDQ test purposes only.

公开(公告)号：EP0929895A1

公开(公告)日：1999-07-21

申请号：EP97910744.0

申请日：1997-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： HOLST, John, Christian ,  DRAPER, Donald, A.

IPC: G06F12 ,  G11C5 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29 ,  H03K3 ,  H03K5 ,  H03L7

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

公开(公告)号：EP0543408B1

公开(公告)日：1998-10-07

申请号：EP92119825.5

申请日：1992-11-20

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kushiyama, Natsuki, c/o Intellectual Property Div. ,  Furuyama, Tohru, c/o Intellectual Property Div. ,  Numata, Kenji, c/o Intellectual Property Div.

IPC: G11C29/00

CPC classification number: G11C29/025 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/5004 ,  G11C2029/5006

公开(公告)号：EP0836196A2

公开(公告)日：1998-04-15

申请号：EP97117402.4

申请日：1997-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： San, Kemal T. ,  Kaya, Cetin ,  Mehrad, Freidoon

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/3409 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

Abstract: A system for testing and adjusting threshold voltages in flash EEPROMs is disclosed. The system includes a memory cell array (5) comprising a plurality of cell columns. Each cell column includes a plurality of memory cells (10). Each memory cell (10) has a control gate terminal (14), a drain terminal (12) and a source terminal 11. A control system comprising a wordline decoder (16), a column decoder (19) and a microprocessor (21) applies selected voltages to the respective terminals of the memory cells (10), and selects one of the plurality of cell columns for compaction verification. A detector (30) determines whether any one of the memory cells (10) of the selected cell column has a threshold voltage below a predetermined positive voltage, and supplies an output signal to the control system. The control system increases respective threshold voltages of the memory cells (10) of the selected cell column in response to the output signal of the detector (30).

Abstract translation: 公开了一种用于测试和调整闪速EEPROM中的阈值电压的系统。 该系统包括包括多个单元列的存储单元阵列（5）。 每个单元列包括多个存储单元（10）。 每个存储单元（10）具有控制栅极端子（14），漏极端子（12）和源极端子11.一种包括字线解码器（16），列解码器（19）和微处理器（21）的控制系统， 将选择的电压施加到存储器单元（10）的各个端子，并且选择多个单元格列之一进行压缩验证。 检测器（30）确定所选单元列的存储单元（10）中的任何一个是否具有低于预定正电压的阈值电压，并将输出信号提供给控制系统。 响应于检测器（30）的输出信号，控制系统增加所选单元列的存储单元（10）的相应阈值电压。

公开(公告)号：EP0616335A3

公开(公告)日：1998-04-15

申请号：EP94101897

申请日：1994-02-08

Applicant: FUJITSU LTD

Inventor： KUMAKURA SINSUKE ,  YAMAZAKI HIROKAZU ,  WATANABE HISAYOSHI ,  KASA YASUSHI

IPC: G01R31/28 ,  G11C5/14 ,  G11C7/06 ,  G11C16/06 ,  G11C17/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  H01L21/8247 ,  H01L27/115

CPC classification number: G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

公开(公告)号：EP0753859A1

公开(公告)日：1997-01-15

申请号：EP95830302.6

申请日：1995-07-14

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Sali, Mauro ,  Dallabora, Marco ,  Carrera, Marcello

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/3459 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/3454 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006

Abstract: A method for setting the threshold voltage of a reference memory cell (RMC) of a memory device is described, the reference memory cell (RMC) being used as a reference current generator for generating a reference current which is compared by a sensing circuit (1,2,3) of the memory device with currents sunk by memory cells to be sensed, belonging to a memory matrix (MM) of the memory device. The method comprises a first step in which the reference memory cell (RMC) is submitted to a change in its threshold voltage, and a second step in which the threshold voltage of the reference memory cell (RMC) is verified. The second step provides for performing a sensing of the reference memory cell (RMC) using a memory cell (MC) with known threshold voltage (V TUV ) belonging to the memory matrix (MM) as a reference current generator for generating a current (IC) which is compared by the sensing circuit (1,2,3) with the current (IR) sunk by the reference memory cell (RMC).

Abstract translation: 描述了用于设置存储器件的参考存储单元（RMC）的阈值电压的方法，参考存储单元（RMC）用作参考电流发生器，用于产生参考电流，该参考电流由感测电路（1 ，2,3）的存储器件，存储器件的存储器矩阵（MM）属于存储器器件的存储器矩阵（MM）。 该方法包括第一步骤，其中参考存储器单元（RMC）被提交到其阈值电压的改变，以及第二步骤，其中验证参考存储单元（RMC）的阈值电压。 第二步提供使用具有属于存储矩阵（MM）的已知阈值电压（VTUV）的存储单元（MC）作为参考电流发生器来执行对参考存储单元（RMC）的感测作为参考电流发生器，用于产生电流（IC） 其通过感测电路（1,2,3）与由参考存储器单元（RMC）沉没的当前（IR）进行比较。

公开(公告)号：EP0488612B1

公开(公告)日：1996-06-26

申请号：EP91310807.2

申请日：1991-11-25

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： Slemmer, William Carl

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/5006

公开(公告)号：EP0595775A1

公开(公告)日：1994-05-04

申请号：EP93830134.8

申请日：1993-04-01

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Cappelletti, Paolo Giuseppe ,  Ravazzi, Leonardo

IPC: G11C29/00 ,  H01L21/66

CPC classification number: G11C29/50004 ,  G06F2201/81 ,  G11C16/04 ,  G11C29/50 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A method employing a test structure (10) identical to the memory array whose gate oxide or interpoly dielectric quality is to be determined, except for the fact that the cells are connected electrically (13-15, 17, 18, 19-21) parallel to one another. The test structure is subjected to electrical stress of such a value and polarity as to extract electrons from the floating gate of the defective-gate-oxide or defective-interpoly-dielectric cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide or interpoly dielectric of EPROM, EEPROM and flash-EEPROM memories.

Abstract translation: 一种方法采用测试结构（10）相同的到所述存储器阵列，其栅氧化物或电介质间（interpoly）质量将被确定，除了在平行所述细胞电连接的factthat（13-15，17，18，19-21） 彼此。 测试结构进行求值和极性，以从有缺陷的栅氧化物或缺陷-间（interpoly）电介质单元的浮置栅提取电子并因此修改该单元的特性，同时使充电的电应力 无缺陷单元不变。 通过这种方式，只有有缺陷的单元的阈值被改变。 然后，低于阈值的电压被施加到测试结构，和通过细胞中的漏电流，所有这是关系到在结构中的至少一个有缺陷的细胞的存在，进行测量。 的电流 - 电压特性的测量和分析用于确定性采矿提供有缺陷的细胞的数目。 该方法适用于栅极氧化物或EPROM，EEPROM和快闪EEPROM存储器间介电的在线质量控制。