公开(公告)号：EP1915037A1

公开(公告)日：2008-04-23

申请号：EP06781905.2

申请日：2006-07-28

Applicant: FUJIKURA LTD. ,  Kyoei Electric Co., Ltd.

Inventor： MOMOTA, Atsushi ,  TERUNUMA, Ichiro ,  HASEGAWA, Takeshi ,  TAKEMURA, Yasuo, c/o Fujikura Ltd. ,  HATAKEYAMA, Y., c/o Kyoei Electric Co., Ltd. ,  HARADA, H., c/o Kyoei Print Industry Co., Ltd. ,  KATOH, M., c/o Kyoei Print Industry Co., Ltd.

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K3/4691 ,  H05K1/036 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/10303 ,  H05K2203/308 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Provided is a bending rigid printed wiring board which facilitates the mounting of electric parts (realization of a high producibility and high assemblability substrate circuit) and enables spaces to be saved and which can be easily manufactured.
That is, provided is a bending rigid printed wiring board, which is characterized in that a heat resistant resin layer 31 is laminated on a front surface of a hard core material 1 provided so as to contain a gap portion 1A and also on a top surface of the gap portion 1A, in that a heat resistant resin layer 32 is laminated on a rear surface of the core material 1 except the gap portion 1A, in that a conductor layer 4 is laminated and firmly fixed via the heat resistant resin layers 31, 32, and in that the conductor layer 4 is etched, whereby a circuit is formed.

Abstract translation: 提供一种弯曲刚性印刷线路板，其有助于电气部件的安装（实现高可生产性和高可组装性的基板电路），并且能够节省空间并且可以容易地制造。 也就是说，设置弯曲刚性印刷线路板，其特征在于，耐热树脂层31层压在硬芯材料1的前表面上，该硬芯材料1设置成包含间隙部分1A，并且还在顶表面 间隔部分1A的除了间隙部分1A之外的层叠在芯材1的后表面上的耐热树脂层32，通过耐热树脂层31,36牢固地固定导体层4， 32，并且导体层4被蚀刻，从而形成电路。

公开(公告)号：EP1825726A1

公开(公告)日：2007-08-29

申请号：EP04809018.7

申请日：2004-11-30

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (publ)

Inventor： SANDWALL, Johan

IPC: H05K1/14 ,  H05K3/46

CPC classification number: H05K1/024 ,  H05K1/142 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0391 ,  H05K2201/09972 ,  H05K2203/061

Abstract: The invention discloses a PCB (100, 400) with first and second main surfaces (110, 130), the PCB also having a first height, h, said two surfaces and height together defining the volume of the PCB. The PCB comprises layers (430, 434, 438) of a first supporting laminate material, layers (440, 431, 433, 435, 437, 439) of a first conducting material and layers (432, 436) of a first prepreg, said first materials and prepreg having respective dielectrical constants and dissipation factors. In the PCB, a sub-volume of the PCB defined by a sub-area (120) within the first main surface and a sub-height (h’) within said first height together comprise a sub-PCB (320) which comprises at least one layer (330, 334) of a second supporting laminate material, said second laminate material differing from the first laminate material with regard to at least one of the factors dielectrical constant and dissipation factor.

公开(公告)号：EP1667206A1

公开(公告)日：2006-06-07

申请号：EP05257178.3

申请日：2005-11-22

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Borland, William J.

IPC: H01L21/00 ,  H01G4/12 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01L27/013 ,  H05K1/092 ,  H05K3/1291 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/035 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/1126 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49156

Abstract: The invention provides a method of making a capacitor comprising: providing a metallic foil; forming a capacitor dielectric over said metallic foil; forming a first electrode over a portion of said capacitor dielectric, thus forming a component side of said metallic foil; laminating the component side of said metallic foil to a laminate material; and etching said metallic foil outside the boundary of said capacitor dielectric to form a second electrode. Using this method allows the laminate material to prevent etching solutions from coming in contact with and damaging the capacitor dielectric layers.

Abstract translation: 本发明提供一种制造电容器的方法，包括：提供金属箔; 在所述金属箔上形成电容器电介质; 在所述电容器电介质的一部分上形成第一电极，从而形成所述金属箔的部件侧; 将所述金属箔的组件侧层压到层压材料上; 以及在所述电容器电介质的边界之外蚀刻所述金属箔以形成第二电极。 使用该方法允许层压材料防止蚀刻溶液与电容器电介质层接触并损坏电容器电介质层。

公开(公告)号：EP1654915A2

公开(公告)日：2006-05-10

申请号：EP04781137.7

申请日：2004-08-13

Applicant: INTEL CORPORATION

Inventor： MCCALL, James ,  SHYKIND, David

IPC: H05K1/00

CPC classification number: H05K3/10 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/0366 ,  H05K3/0052 ,  H05K2201/0187 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09972 ,  H05K2203/1554 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49798 ,  Y10T428/24058 ,  Y10T428/24917 ,  Y10T428/249935 ,  Y10T428/24994 ,  Y10T428/249943 ,  Y10T428/249946 ,  Y10T442/2926 ,  Y10T442/2992 ,  Y10T442/3065

Abstract: A circuit board is described where the fiberglass fiber pattern as been modified than what is found in conventional FR4 circuit boards. In one embodiment, the sets of fiberglass fibers are disposed in a zig-zag or herringbone manner. In one use, when a pair of conductors are disposed onto or into the board, the material surrounding a first conductor tends to be similar to the material surrounding a second conductor. Doing so may reduce differential to common mode conversion between the conductors.

公开(公告)号：EP1123643B1

公开(公告)日：2005-01-12

申请号：EP99956422.2

申请日：1999-10-05

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： BERGSTEDT, Leif ,  LIGANDER, Per ,  BOUSTEDT, Katarina

IPC: H05K1/03 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/186 ,  H05K1/185 ,  H05K3/386 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49169

Abstract: A compact printed board assembly has a patterned copper-coated substrate (1) with electronic components (5, 12) mounted thereon. Depending on the height of the components, either SBU lacquer (11) or non-flow prepreg (3) and laminate (4) surround the electronic components. This subassembly is then sandwiched between two RC (resin coated) copper foils (8) with the resin (7) facing the components (5, 12) and burying them, thereby providing a new etchable copper surface which can be connected by means of microvias (10) to the embedded components (5, 12).

公开(公告)号：EP1062849A4

公开(公告)日：2004-08-25

申请号：EP99964046

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  LACH LARRY ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  SIMONS EVERETT

IPC: H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/522 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K3/0082 ,  H01F17/0013 ,  H01F41/041 ,  H01F41/046 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2203/0551

Abstract: A method for fabricating circuit board conductors (24A & 24B) generally entails forming a metal layer (24) on a positive-acting photodielectric layer (22), and etching the metal layer to form at least two conductor traces (24A & 24B) that cover separate regions of the photodielectric layer while exposing a third region therebetween. The third region of the photodielectric layer is developed using the two traces as a photomask and removed. Thus, the traces are not only separated by a void (30) formed when the metal layer was etched, but are also separated by the opening (32) formed in the photodielectric layer by the removal of the third region of the photodielectric layer. A ferrite-filled polymer may also be deposited in the void and opening to form a ferrite core (34). Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

公开(公告)号：EP1202300A3

公开(公告)日：2004-06-16

申请号：EP01124177.5

申请日：2001-10-11

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Shimada, Mikinari ,  Nakada, Yasuhiko ,  Nakatani, Seiichi ,  Shiraishi, Seigo ,  Handa, Hiroyuki ,  Ishikawa, Akihiro

IPC: H01G9/00

CPC classification number: H01G9/15 ,  H01G11/48 ,  H01G11/56 ,  H05K1/141 ,  H05K1/162 ,  H05K1/185 ,  H05K2201/0187 ,  H05K2201/0323 ,  H05K2201/0329 ,  H05K2203/0315 ,  Y02E60/13 ,  Y10T29/417

Abstract: In an electrolytic capacitor of the present invention, a dielectric layer 12 is provided on a surface of a valve metal element for an anode 11 having a capacitor forming part 11B and an electrode lead part 11A, and further, a solid electrolyte layer 13 and a charge collecting layer for a cathode 14 are provided in this order thereon. The capacitor forming part 11B and the electrode lead part 11A of the valve metal element for an anode 11 have rough surface layers on their surfaces, and are compressed in the thickness direction of the rough surface layers. Further, a region other than the electrode lead part 11A and the charge collecting element for cathode 14 is molded with a molding material. Exposed portions of the electrode lead part 11A and the charge collecting element for cathode 14 function as electrode terminals, respectively.

公开(公告)号：EP1405446A2

公开(公告)日：2004-04-07

申请号：EP02739953.4

申请日：2002-06-24

Applicant: Viasystems Group, Inc.

Inventor： TOURNE, Joseph, A., A., M.

IPC: H04J1/00

CPC classification number: G02B6/43 ,  G02B6/138 ,  H05K1/0274 ,  H05K3/0008 ,  H05K3/0032 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09918

Abstract: Polymers of differing refraction indices are embedded within a PCB (14) to provide optical connectivity of the PCB (14) with other circuit boards via an optic backplane. The creation of islands of polymer material (12) of refractive index n1 completely surrounded by polymer material (16) with refractive index n2 where n1 has a higher index than n2 allows the islands of n1 indexed polymer to serve as optical waveguides. A process of forming a multi-layered PCB (14) with the optical waveguide islands using successive laminations and using laser ablation to write the optical connection scheme is taught. Further, the use of uniquely marked targets in a copper layer (10, 11) to align the optical waveguides in production is also taught. Additionally, the use of clearing polymer materials and reinforcing polymer voids with prepreg lamination to allow a simple, high tolerance insertion of through-holes is taught.

公开(公告)号：EP1376739A1

公开(公告)日：2004-01-02

申请号：EP03012280.8

申请日：2003-06-11

Applicant: HARRIS CORPORATION

Inventor： Killen, William Dean ,  Pike, Randy T.

IPC: H01P1/203

CPC classification number: H01P7/082 ,  H01P7/084 ,  H05K1/0239 ,  H05K1/024 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/0715

Abstract: A printed circuit for processing radio frequency signals. The printed circuit includes a substrate. The substrate can be a meta material and can include at least one dielectric layer. The dielectric layer can have a first set of dielectric properties over a first region and a second set of dielectric properties over a second region. The dielectric permittivity and/or magnetic permeability of the second set of dielectric properties can be different than the first set of dielectric properties. The printed circuit also can include a single port resonant line and a ground coupled to the substrate. The dielectric properties can be controlled to adjust the size of the resonant line. The dielectric properties also can be controlled to adjust an impedance, quality factor and/or capacitance on the resonant line. Resonant characteristics of the resonant line can be distributed through the substrate.

Abstract translation: 一种用于处理射频信号的印刷电路。 印刷电路包括基板。 衬底可以是间位材料，并且可以包括至少一个电介质层。 电介质层可以在第一区域上具有第一组介电特性，在第二区域上可具有第二组介电特性。 第二组介电特性的介电常数和/或磁导率可以不同于第一组介电特性。 印刷电路还可以包括单端口谐振线路和耦合到衬底的地线。 可以控制介电特性以调节谐振线的尺寸。 也可以控制介电特性以调节谐振线路上的阻抗，品质因数和/或电容。 谐振线路的谐振特性可以分布在基板上。

公开(公告)号：EP1376736A1

公开(公告)日：2004-01-02

申请号：EP03012278.2

申请日：2003-06-11

Applicant: HARRIS CORPORATION

Inventor： Rumpf, Raymond Charles ,  Killen, William Dean ,  Pike, Randy T.

IPC: H01P1/02

CPC classification number: H01P5/02 ,  H01P1/02 ,  H05K1/024 ,  H05K1/165 ,  H05K2201/0187 ,  H05K2201/09263 ,  H05K2201/09727

Abstract: A circuit for processing radio frequency signals. The circuit can include a substrate board that has at least one dielectric layer (100) having a first set of substrate properties over a first region (102). The first set of substrate properties can include a first permittivity and a first permeability. A second region (140) can be provided with a set of second substrate properties. The second region can have a second set of substrate properties including a second permittivity and a second permeability. The second permittivity can be different than the first permittivity and/or the second permeability can be different than the first permeability. A first transmission line (102) having at least one discontinuity can be coupled to the second region (108). The discontinuity can include a bend, corner, non-uniformity, break in the transmission line, or a junction between the first transmission line and a second transmission line.

Abstract translation: 一种用于处理射频信号的电路。 电路可以包括衬底板，其具有在第一区域（102）上具有第一组衬底特性的至少一个电介质层（100）。 第一组衬底特性可以包括第一介电常数和第一磁导率。 第二区域（140）可以具有一组第二基板特性。 第二区域可以具有包括第二介电常数和第二渗透率的第二组衬底特性。 第二介电常数可以不同于第一介电常数和/或第二磁导率可以不同于第一磁导率。 具有至少一个不连续性的第一传输线（102）可以耦合到第二区域（108）。 不连续性可以包括传输线中的弯曲，拐角，不均匀性，断裂或第一传输线与第二传输线之间的连接。